AD1843 Ver la hoja de datos (PDF) - Analog Devices
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AD1843 Datasheet PDF : 64 Pages
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AD1843
ANALOG OUTPUT
Min
LOUT1 Full-Scale Output Voltage
(RMS Values Assume Sine Wave Input)
1.8
LOUT2 Full-Scale Single-Ended Output Voltage
(RMS Values Assume Sine Wave Input)
1.8
LOUT2 Full-Scale Differential Output Voltage
(RMS Values Assume Sine Wave Input)
3.6
LOUT1 Output Impedance*
LOUT2 Output Impedance*
LOUT1 External Load Impedance*
10
LOUT2 External Load Impedance*
2
MOUT External Load Impedance*
10
HPOUT External Load Impedance*
16
HPOUT THD+N (Referenced to Full Scale, 32 Ω External Load Impedance)
Output Capacitance*
External Load Capacitance*
CMOUT
2.10
External CMOUT Load Current*
CMOUT Output Impedance*
Mute Click* (Muted Output Minus Unmuted Midscale DAC1 and DAC2 Outputs)
Typ
Max
0.707
2.0
2.2
0.707
2.0
2.2
1.414
4.0
4.4
600
1
32
0.10
–60
15
100
2.25
2.40
10
4
±5
Units
V rms
V p-p
V rms
V p-p
V rms
V p-p
Ω
Ω
kΩ
kΩ
kΩ
Ω
%
dB
pF
pF
V
µA
kΩ
mV
SYSTEM SPECIFICATIONS
System Frequency Response Ripple* (Line-In to Line-Out)
Differential Nonlinearity*
Phase Linearity Deviation*
Max
Units
1.0
dB
±1
Bit
5
Degrees
STATIC DIGITAL SPECIFICATIONS
High-Level Input Voltage (VIH)
Digital Inputs, Except SCLK
XTALI and SCLK
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH)
Low-Level Output Voltage (VOL)
Input Leakage Current (GO/NOGO Tested)
Output Leakage Current (GO/NOGO Tested)
Min
Max
Units
2.0
VDD+ 0.3 V
2.4
VDD+ 0.3 V
–0.3
0.8
V
2.4
V
0.4
V
–10
10
µA
–10
10
µA
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE AND DIGITAL SUPPLY RANGE)
Min
Typ
Max
Units
Serial Data Frame Sync [SDFS] Period (t1)
(Master Mode, FRS = 1 [16 Slots per Frame], SCF = 0 [SCLK = 12.288 MHz])
20.833
µs
Frame Sync [SDFS] HI Pulse Width (t2)
80
ns
Clock [SCLK] to Frame Sync [SDFS] Propagation Delay (tPD1)
15
ns
Data [SDI] Input Setup Time to SCLK (tS)
10
ns
Data [SDI] Input Hold Time from SCLK (tH)
10
ns
Clock [SCLK] to Output Data [SDO] Valid (tDV)
15
ns
Clock [SCLK] to Output Data [SDO] Three-State [High-Z] (tHZ)
15
ns
Clock [SCLK] to Time Slot Output [TSO] Propagation Delay (tPD2)
15
ns
RESET and PWRDWN LO Pulse Width (tRPWL)
100
ns
SCLK
SDFS
SDI
SDO
t2
tPD1
tS tH
BIT 15
BIT 15
BIT 14
tDV
BIT 14
REV. 0
BIT 0
tHZ
BIT 0
SCLK
SDFS
SDI OR SDO
TSO
tPD1
15 14 13
RESET
PWRDWN
Figure 1. Timing Diagrams
–5–
tRPWL
t1
3 2 1 0 15 14 13
LAST
VALID
TIME SLOT
tPD2
15 1413
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