74F378 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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74F378

Parallel D-Type Register with Enable

Fairchild Semiconductor 

Unit Loading/Fan Out

Pin Names

Description

E

D0–D5

CP

Q0–Q5

Enable Input (Active LOW)

Data Inputs

Clock Pulse Input (Active Rising Edge)

Outputs

U.L.

HIGH/LOW

1.0/1.0

1.0/1.0

1.0/1.0

50/33.3

Input IIH/IIL

Output IOH/IOL

20 µA/−0.6 mA

20 µA/−0.6 mA

20 µA/−0.6 mA

−1 mA/20 mA

Functional Description

The 74F378 consists of six edge-triggered D-type flip-flops

with individual D inputs and Q inputs. The Clock (CP) and

Enable (E) inputs are common to all flip-flops.

When the E input is LOW, new data is entered into the reg-

ister on the LOW-to-HIGH transition of the CP input. When

the E input is HIGH the register will retain the present data

independent of the CP input.

Truth Table

Inputs

E

H

CP



Dn

X

L



H

L



L

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Clock Transition

Output

Qn

No Change

H

L

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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