100
TA = +25°C
ALL DIGITAL INPUTS
10
TIED TOGETHER
1.0
VDD = +5V
0.1
0.01
0.001
VDD = +3V
0.0001
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
LOGIC INPUT VOLTAGE – Volts
Figure 13. Supply Current vs. Logic Input Voltage
80
60
VDD = +5V ±0.5VP
VREFH = +2V
CODE = 80H
TA = +25°C
40
20
0
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 14. Power Supply Rejection vs. Frequency
100
2V 90
OUT1
0V
5V 10
CS
0%
0V
VDD = +5V
VREF = +2V
TIME – 1µs/DIV
Figure 15. Large-Signal Settling Time
AD8801/AD8803
OUTPUT1: OOH → FFH
VDD = +5V
100
90
VREF = +2V
f = 500kHz
10
0%
TIME – 0.2µs/DIV
Figure 16. Adjacent Channel Clock Feedthrough
100
90
OUT1
10mV/DIV
OUTPUT1: 7FH → 80H
VDD = +5V
VREF = +2V
CS
5V/DIV 10
0%
TIME – 0.2µs/DIV
Figure 17. Midscale Transition
0.01
0.005
VDD = +4.5V
VREF = +4.5V
SS = 162 PCS
VREFL = 0V
0
–0.005
–0.01
0
150
300
450
600
HOURS OF OPERATION AT 150°C
Figure 18. Zero-Scale Error Accelerated by Burn-In
REV. A
–7–