HMP8156ACN Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
fabricante
HMP8156ACN Datasheet PDF : 34 Pages
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Pinout
HMP8154, HMP8156A
HMP8154/HMP8156A
(PQFP)
TOP VIEW
VAA
VAA
Y/G
GND
VAA
GND
C/B
GND
VAA
GND
NTSC/PAL1
GND
VAA
GND
NTSC/PAL2
GND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P8
P9
P10
P11
P12
P13
GND
CLK2
VAA
CLK
P14
P15
VSYNC
HSYNC
FIELD
BLANK
Pin Descriptions
PIN
NAME
PIN
NUMBER
P0-P15
58, 55-43,
38, 37
P16-P23
32-27, 23,
22
RESV
21
FIELD
34
HSYNC
35
VSYNC
36
BLANK
33
INPUT/
OUTPUT
I
DESCRIPTION
Pixel input pins. See Table 1. Any pixel inputs not used should be connected to GND.
I
Overlay or pixel inputs. See Table 1. Any overlay or pixel inputs not used should be connect-
ed to GND.
I
This pin is reserved and should be connected to VCC or GND.
O
FIELD output. The field output indicates that the encoder is outputting the odd or even video
field. The polarity of FIELD is programmable.
Horizontal sync input/output. As an input, this pin must be asserted during the horizontal
sync intervals. If it occurs early, the line time will be shortened. If it occurs late, the line
I/O
time will be lengthened by holding the outputs at the front porch level. As an output, it is
asserted during the horizontal sync intervals. The polarity of HSYNC is programmable. If
not driven, the circuit for this pin should include a 4-12kΩ pull up resistor connected to
VAA.
Vertical sync input/output. As an input, this pin must be asserted during the vertical sync
intervals. If it occurs early, the field time will be shortened. If it occurs late, the field time
I/O
will be lengthened by holding the outputs at the blanking level. As an output, it is asserted
during the vertical sync intervals. The polarity of VSYNC is programmable. If not driven,
the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA.
Composite blanking input/output. As an input, this pin must be asserted during the hori-
I/O
zontal and vertical blanking intervals. As an output, it is asserted during the horizontal and
vertical blanking intervals. The polarity of BLANK is programmable. If not driven, the circuit
for this pin should include a 4-12kΩ pull up resistor connected to VAA.
24
4343.4
November 4, 2005
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