Part Name
TC74HC279AF
Description
Other PDF
PDF
page
8 Pages
File Size
276 kB
MFG CO.
Toshiba
HOME >>> Toshiba >>> TC74HC279AF PDF
TC74HC279AF Datasheet - Toshiba
Toshiba
Quad S-R Latch
The TC74HC279A is a high speed CMOS QUAD S-R LATCH fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.
Each latch has an independent Q output and Set and Reset inputs. S and R are active low. When S input is low, the Q output goes high and when R input is low, the Q output goes low. When both S and R are low, S takes precedence resulting Q = low. When both of S and R are held high, Q output doesn’t change.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features
• High speed: tpd = 12 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼ − tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
• Pin and function compatible with 74LS279
Share Link: 