DESCRIPTION
The SY10/100ELT21 are single differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the ELT21 ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical.
The VBB output allow differential single-ended, or AC coupled interface to the device. If used, the VBB output should be bypassed to VCC with a 0.01µF capacitor.
The ELT21 is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels.

FEATURES
■ 2.5ns typical propagation delay
■ Low power
■ Differential PECL inputs
■ 24mA TTL outputs
■ Flow-through pinouts
■ Available in 8-pin SOIC package