GENERAL DESCRIPTION
The DDR400 SDRAM is a high-speed CMOS, dynamic random-access memory that operates at a frequency of 200 MHz (tCK=5ns) with a peak data transfer rate of 400Mb/s. DDR400 continues to use the JEDEC standard SSTL_2 interface and the 2n-prefetch architecture.

FEATURES
• 200 MHz Clock, 400 Mb/s/p data rate
• VDD = +2.65V ±0.10V
• VDDQ = +2.65V ±0.10V
• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• tRAS lockout (tRAP = tRCD)