General description

   The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.

Features and benefits

• Complies with JEDEC standard no. 7A

• Input levels:

   • For 74HC173: CMOS level

   • For 74HCT173: TTL level

• Gated input enable for hold (do nothing) mode

• Gated output enable control mode

• Edge-triggered D-type register

• Asynchronous master reset

• ESD protection:

   • HBM JESD22-A114F exceeds 2000 V

   • MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and -40 °C to +125 °C