General description
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity.
   
Features and benefits
• Two sets of high speed parallel registers with positive
    edge-triggered D-type flip-flops
• 5 V I/O compatible
• Ideal where high speed, light loading or increased
    fan-in are required with MOS microprocessors
• Bus hold data inputs eliminate the need for external
    pull-up resistors to hold unused inputs
• Live insertion and extraction permitted
• Power-up 3-state
• Power-up reset
• Output capability: +12 mA to −12 mA
• Outputs include series resistance of 30 Ω making external
    termination resistors unnecessary
• Latch-up protection:
    – JESD78: exceeds 500 mA
• ESD protection:
    – MIL STD 883, method 3015: exceeds 2000 V
    – MM: exceeds 200 V