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5962-8950502YX Datasheet - Semiconductor Corporation
Semiconductor Corporation
FEATURES
◾ Implements the MIL-STD-1750A Instruction Set
Architecture for Memory Management and
Protection of up to 1 Megaword. All mapping
memory (10,240 bits) for both the MMU and
BPU functions are included on the chip.
◾ Designed to interface memory to the
PACE1750A/AE 16-bit, 40 MHz processor.
Systems can be designed where no WAIT
states are required up to 40 MHz clock rates
when using these PACE products.
◾ System performance and device count are
optimized when used with the PACE1754
Processor Interface Circuit (PIC).
◾ Provides the following additional functions:
— EDAC, Error Detection and Correction—or
parity generation and detection
— Correct data register—for diagnostics
— First memory failing address register
— Illegal address error detection—
programmable
— Multi-Master arbitration
◾ 8-bit extended address latches and drivers on
chip
◾ Information bus and EDAC transceivers on chip
◾ 20, 30 and 40 MHz operation over the Military
Temperature Range
◾ Single 5V ± 10% Power Supply
◾ Power Dissipation over Military Temperature
Range (PD Outputs Open)
< 0.20 watts at 20 MHz
< 0.30 watts at 30 MHz
< 0.40 watts at 40 MHz
◾ Available in:
— 64-Pin DIP or Gull Wing (50 Mil Pin centers)
— 68-Pin Pin Grid Array (PGA) (100 Mil centers)
— 68-Lead Quad Pack (Leaded Chip Carrier)
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