GENERAL DESCRIPTION
54S416T is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x 16 bits. Using pipelined architecture.
54S416T delivers a data bandwidth of up to 400M bytes per second (-5). For different application, 54S416T is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200 MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For handheld device application.

FEATURES
• 3.3V ±0.3V power supply
• 1048576 words x 4 banks x 16 bits organization
• Burst read,single write operation
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8, and full page
• Sequential and Interleave burst
• Byte data controlled by DQM
• Power-down Mode
• Auto-precharge and controlled precharge
• 4K refresh cycles/64 mS
• Interface: LVTTL
• Packaged in TSOP II 54-pin, 400 mil - 0.80