TMC22053AKHC View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

MFG CO.

TMC22053AKHC

Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit

Fairchild Semiconductor 

TMC22x5yA

PRODUCT SPECIFICATION

Control Register Definitions (continued)

Input Processor Control (01)

7

6

5

Reserved

IPMUX

IP8B

4

TDEN

3

TBLK

2

IPCMSB

1

ABMUX

0

CKSEL

Reg Bit

01

7

01

6

Name

Reserved

IPMUX

01

5

01

4

IP8B

TDEN

01

3

TBLK

01

2

01

1

01

0

IPCMSB

ABMUX

CKSEL

Description

Reserved, set to zero.

Input mux control. Used to select the Video Input Processor, D1, or D2 data

as the VA input to the input processor.

VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is

set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set

HIGH. For YC inputs, the luma data must be passed through the VA input and

chroma through the VB input.

IPMUX should be set LOW for line locked composite inputs.

8 bit input format. Bottom two bits of inputs VIDEOA9-0 and VIDEOB9-0 are

set to zero when HIGH.

TRS detect enable. When HIGH, the TRS words embedded in incoming

video are used to reset the horizontal and vertical state machines. When LOW

the externally provided or internally generated HSYNC and VSYNC are used

to reset the horizontal and vertical state machines.

TRS blank enable. Blanks the TRS and AUX data words when HIGH. For line

locked and D1 data, the TRS and AUX data words are set to the luma and

chroma blanking levels as appropriate. For D2 (4*fSC) data, the TRS and

AUX data words are set to the sync tip level.

Chroma input msb invert. The msb of the chroma or CBCR data are inverted

when HIGH.

AB mux control. Selects the primary and secondary inputs to the decoder

from the DA and DB outputs of the input processor. When ABMUX is LOW,

DA is selected as the primary and DB as the secondary decoder input.

Input clock rate select. Set HIGH for line locked clocks and LOW for

subcarrier locked clocks. Line locked clocks should be at twice the pixel data

rate, and the subcarrier clock should be at four times the subcarrier

frequency.

12

REV. 1.0.0 2/4/03

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