UPD705100 View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
UPD705100 Datasheet PDF : 66 Pages
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µPD705100
(6) Bus hold timing (1/2)
(a) When the internal operating frequency is 75 to 100 MHz
Parameter
Symbol
CSn output delay (relative to BCLK↑) 16 tDKCS
CSn output hold time
(relative to BCLK↑)
17 tHKCS
READY set time (relative to BCLK↑) 20 tSRYK
READY hold time (relative to BCLK↑) 21 tHKRY
HLDRQ set time (relative to BCLK↑) 32 tSHQK
HLDRQ hold time (relative to BCLK↑) 33 tHKHQ
HLDAK output delay
(relative to BCLK↑)
HLDAK output hold time
(relative to BCLK↑)
Address delay
(from active, relative to BCLK↑)
Address delay
(from float, relative to BCLK↑)
Data delay
(from active, relative to BCLK↑)
Data delay
(from float, relative to BCLK↑)
BCYST delay
(from active, relative to BCLK↑)
BCYST delay
(from float, relative to BCLK↑)
34 tDKHA
35 tHKHA
36 tHZKA
37 tLZKA
38 tHZKD
39 tLZKD
40 tHZKBC
41 tLZKBC
Conditions
When φ = 3f
When φ = 2f
Unit
MIN. MAX. MIN. MAX.
2
13
2
13
ns
2
13
2
13
ns
10
9
ns
0
0
ns
6
6
ns
2
1
ns
2
13
2
13
ns
2
13
2
13
ns
3
20
3
20
ns
2
13
2
10
ns
3
20
3
20
ns
2
13
2
10
ns
3
20
3
20
ns
2
13
2
10
ns
55
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