M41T64LC6F(2019) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M41T64LC6F
(Rev.:2019)

Low-power serial real-time clocks (RTCs) with alarm

STMicroelectronics 

M41T62, M41T64, M41T65

READ mode

2.1.5

Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by

the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is

addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of

the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way

that the SDA line is a stable Low during the high period of the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter

by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the

transmitter must leave the data line high to enable the master to generate the STOP condition.

Figure 11. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

Figure 12. Acknowledgement sequence

START

SCL FROM

MASTER

1

2

DATA OUTPUT

BY TRANSMITTER

MSB

DATA OUTPUT

BY RECEIVER

CLOCK PULSE FOR

ACKNOWLEDGEMENT

8

9

LSB

2.2

READ mode

In this mode the master reads the M41T6x slave after setting the slave address (see Figure 14. READ mode

sequence). Following the WRITE mode control bit (R/W̅ =0) and the acknowledge bit, the word address 'An' is

written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the

READ mode control bit (R/W̅ =1). At this point the master transmitter becomes the master receiver. The data byte,

which was addressed is transmitted and the master receiver sends an acknowledge bit to the slave transmitter.

The address pointer is only incremented on reception of an acknowledge clock. The M41T6x slave transmitter

now places the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte

and the address pointer is incremented to “An+2.”

This cycle of reading consecutive addresses continues until the master receiver sends a STOP condition to the

slave transmitter.

DS3840 - Rev 24

page 8/42

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