EVAL-ADM1068LQEB View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-ADM1068LQEB

Super Sequencer™ and Monitor

Analog Devices 

Preliminary Technical Data

1

2

3

4

56 7

8 9 10 11 12

S

SLAVE

ADDRESS

W

A

COMMAND 0xFD

(BLOCK READ)

A

S

SLAVE

ADDRESS

RA

BYTE

COUNT

A

DATA

1

A

13 14

DATA

32

A

P

Figure 35. Block Read from EEPROM or RAM

Error Correction

The ADM1068 provides the option of issuing a PEC (packet

error correction) byte after a write to RAM, a write to EEPROM,

a block write to RAM/EEPROM, or a block read from RAM/

EEPROM. This enables the user to verify that the data received

by or sent from the ADM1068 is correct. The PEC byte is an

optional byte sent after that last data byte has been written to or

read from the ADM1068. The protocol is as follows:

1. The ADM1068 issues a PEC byte to the master. The master

checks the PEC byte and issues another block read, if the

PEC byte is incorrect.

ADM1068

2. A no acknowledge (NACK) is generated after the PEC byte

to signal the end of the read.

Note that the PEC byte is calculated using CRC-8. The frame

check sequence (FCS) conforms to CRC-8 by the polynomial

C(x) = x8 + x2 + x1 + 1

See the SMBus 1.1 specification for details.

An example of a block read with the optional PEC byte is

shown in Figure 36.

1

2

3

4

56 7

8 9 10 11 12

S

SLAVE

ADDRESS

W

A

COMMAND 0xFD

(BLOCK READ)

A

S

SLAVE

ADDRESS

R

A

BYTE

COUNT

A

DATA

1

A

13 14 15

DATA

32

A

PEC A P

Figure 36. Block Read from EEPROM or RAM with PEC

Rev. PrB | Page 25 of 28

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