LTC6992HS6-4-WTRMPBF View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
LTC6992HS6-4-WTRMPBF Datasheet PDF : 34 Pages
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LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25μA to 20μA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
ISET < 1.25µA. At approximately 500nA, the oscillator out-
put will be frozen in its current state. The output could halt
in a high or low state. This avoids introducing short pulses
while frequency modulating a very low frequency output.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Pulse Width Modulation Bandwidth and Settling Time
The LTC6992 has a wide PWM bandwidth, making it
suitable for a variety of feedback applications. Figure 10
shows that the frequency response is flat for modulation
frequencies up to nearly 1/10 of the output frequency.
Beyond that point, some peaking may occur (depending
on NDIV and average duty cycle setting).
Duty cycle settling time depends on the master oscillator
frequency. Following a ±80mV step change in VMOD, the
duty cycle takes approximately eight master clock cycles
(8 • tMASTER) to settle to within 1% of the final value.
Examples are shown in Figure 11a and Figure 11b.
10
÷4, 50%
5
÷16
÷1, 50%
0
÷1, 80%
–5
÷4, 15%
–10
–15
–20
0.001
0.01
0.1
fMOD/fOUT (Hz/Hz)
1
6992 F10
Figure 10. PWM Frequency Response
VMOD
0.1V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
VMOD
0.1V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
V+ = 3.3V
10µs/DIV
DIVCODE = 0
RSET = 200k
VMOD = 0.3V ±40mV
6992 F11a
V+ = 3.3V
10µs/DIV
DIVCODE = 0
RSET = 200k
VMOD = 0.5V ±40mV
6992 F11b
(a) 25% Duty Cycle
(b) 50% Duty Cycle
Figure 11. PWM Settling Time
22
For more information www.analog.com
Rev. D
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