LTC6992HS6-4-WTRMPBF View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

LTC6992HS6-4-WTRMPBF

TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)

Analog Devices 

LTC6992-1/LTC6992-2/

LTC6992-3/LTC6992-4

APPLICATIONS INFORMATION

a large RSET resistor. POL = 0 and NDIV = 4 requires

DIVCODE = 1. Using Table 1, choose the R1 and R2 values

to program DIVCODE = 1.

Step 4: Select RSET

Calculate the correct value for RSET using Equation (1b).

RSET

=

1MHz • 50k

4 • 20kHz

=

625k

Since 625k is not available as a standard 1% resistor,

substitute 619k if a 0.97% frequency shift is acceptable.

Otherwise, select a parallel or series pair of resistors such

as 309k and 316k to attain a more precise resistance.

The completed design is shown in Figure 7.

VMOD

MOD OUT

LTC6992-4

GND

V+

SET

RSET

625k

DIV

6992 F07

2.25V TO 5.5V

R1

976k

DIVCODE = 1

R2

102k

Figure 7. 20kHz PWM Oscillator

Figure 8 demonstrates the worst-case impact of this varia-

tion (if VSET is at its 0.97V or 1.03V limits).

This error is in addition to the inherent PWM duty cycle

accuracy spec ΔD (±4.5%), so care should be taken if

accuracy at high duty cycles (VMOD near 0.9V) is critical.

Sensitivity to ΔVSET can be eliminated by making VMOD

proportional to VSET. For example, Figure 9 shows a

simple circuit for generating an arbitrary duty cycle. The

equation for duty cycle does not depend on VSET at all.

100

90

80

70

60

50

40

30

20

10

0

0

∆VSET = –30mV

∆VSET = 0mV

∆VSET = 30mV

0.2

0.4

0.6

0.8

1

VMOD (V)

6992 F08

Figure 8. Duty Cycle Variation Due to ∆VSET

Duty Cycle Sensitivity to ΔVSET

The output duty cycle is proportional to the ratio of VMOD/

VSET. Since VSET can vary up to ±30mV from 1V it can

effectively gain or attenuate VMOD, as shown below when

ΔVSET is added to the equation.

D=

VMOD

1

−

0.8 • (VSET + ∆VSET ) 8

For many designs, the absolute VMOD to duty cycle accu-

racy is not critical. For others, making the simplifying

assumption of ΔVSET = 0V creates the potential for addi-

tional duty cycle error, which increases with VMOD, reach-

ing a maximum of 3.4% if ΔVSET = –30mV.

∆D ≅ −

VMOD

800mV

•

∆VSET

VSET

≅

−

⎛⎜D

⎝

IDEAL

+

1

8

⎞

⎟

⎠

•

∆VSET

VSET

MOD OUT

LTC6992-X

GND

V+

2.25V TO 5.5V

R1

SET

DIV

RSET1

6992 F09

R2

RSET2

D= 5 •

RSET2

−1

4 RSET1 + RSET2 8

Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator

For more information www.analog.com

Rev. D

21

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