LTC6992HS6-2 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

LTC6992HS6-2

TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)

Analog Devices 

LTC6992-1/LTC6992-2/

LTC6992-3/LTC6992-4

OPERATION

Table 1. DIVCODE Programming

DIVCODE

POL

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

1

9

1

10

1

11

1

12

1

13

1

14

1

15

1

NDIV

1

4

16

64

256

1024

4096

16384

16384

4096

1024

256

64

16

4

1

RECOMMENDED fOUT

62.5kHz to 1MHz

15.63kHz to 250kHz

3.906kHz to 62.5kHz

976.6Hz to 15.63kHz

244.1Hz to 3.906kHz

61.04Hz to 976.6Hz

15.26Hz to 244.1Hz

3.815Hz to 61.04Hz

3.815Hz to 61.04Hz

15.26Hz to 244.1Hz

61.04Hz to 976.6Hz

244.1Hz to 3.906kHz

976.6Hz to 15.63kHz

3.906kHz to 62.5kHz

15.63kHz to 250kHz

62.5kHz to 1MHz

R1 (kΩ)

Open

976

976

1000

1000

1000

1000

1000

887

681

523

392

280

182

102

Short

R2 (kΩ)

Short

102

182

280

392

523

681

887

1000

1000

1000

1000

1000

976

976

Open

VDIV/V+

≤0.03125 ±0.015

0.09375 ±0.015

0.15625 ±0.015

0.21875 ±0.015

0.28125 ±0.015

0.34375 ±0.015

0.40625 ±0.015

0.46875 ±0.015

0.53125 ±0.015

0.59375 ±0.015

0.65625 ±0.015

0.71875 ±0.015

0.78125 ±0.015

0.84375 ±0.015

0.90625 ±0.015

≥0.96875 ±0.015

Table 1 offers recommended 1% resistor values that accu-

rately produce the correct voltage division as well as the

corresponding NDIV and POL values for the recommended

resistor pairs. Other values may be used as long as:

1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-

tor tolerances and temperature effects).

2. The driving impedance (R1||R2) does not exceed

500kΩ.

If the voltage is generated by other means (i.e. the output

of a DAC) it must track the V+ supply voltage. The last

column in Table 1 shows the ideal ratio of VDIV to the

supply voltage, which can also be calculated as:

VDIV

V+

= DIVCODE+ 0.5

16

±1.5%

For example, if the supply is 3.3V and the desired DIVCODE

is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.

Figure 2 illustrates the information in Table 1, showing

that NDIV is symmetric around the DIVCODE midpoint.

16

1000

POL BIT = 0

POL BIT = 1

0

100

1

10

2

3

1

4

5

0.1

6

15

14

13

12

11

10

9

0.01

78

0.001

0V

0.5• V+

INCREASING VDIV

Figure 2. Frequency Range and POL Bit vs DIVCODE

V+

6992 F02

For more information www.analog.com

Rev. D

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