LTC6992HS6-2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
LTC6992HS6-2 Datasheet PDF : 34 Pages
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LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
The LTC6992 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
fMASTER
=
1
tMASTER
=
1MHz
•
50k
•
ISET
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
fMASTER
=
1
tMASTER
=
1MHz • 50k
RSET
From this equation, it is clear that VSET drift will not affect
the output frequency when using a single program resis-
tor (RSET). Error sources are limited to RSET tolerance and
the inherent frequency accuracy ΔfOUT of the LTC6992.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25μA and 20μA).
The LTC6992 includes a programmable frequency divider
which can further divide the frequency by 1, 4, 16, 64,
256, 1024, 4096 or 16384 before driving the OUT pin.
The divider ratio NDIV is set by a resistor divider attached
to the DIV pin.
fOUT
=
1
tOUT
=
1MHz • 50k
NDIV
•
ISET
VSET
With RSET in place of VSET/ISET the equation reduces to:
fOUT
=
1
tOUT
=
1MHz • 50k
NDIV • RSET
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit
A/D converter that determines the DIVCODE value.
DIVCODE programs two settings on the LTC6992:
1. DIVCODE determines the output frequency divider set-
ting, NDIV.
2. DIVCODE determines the output polarity, via the POL
bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 2.
2.25V TO 5.5V
V+
LTC6992
R1
DIV
R2
GND
6992 F01
Figure 1. Simple Technique for Setting DIVCODE
For more information www.analog.com
Rev. D
15
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