LTC6994CS6-1 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

LTC6994CS6-1

TimerBlox: Delay Block/Debouncer

Analog Devices 

LTC6994-1/LTC6994-2

OPERATION

If the voltage is generated by other means (i.e., the output

of a DAC) it must track the V+ supply voltage. The last

column in Table 1 shows the ideal ratio of VDIV to the

supply voltage, which can also be calculated as:

VDIV

V+

=

DIVCODE + 0.5

16

± 1.5%

For example, if the supply is 3.3V and the desired DIVCODE

is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.

Figure 2 illustrates the information in Table 1, showing

that NDIV is symmetric around the DIVCODE midpoint.

Table 1. DIVCODE Programming

DIVCODE

POL

NDIV

0

0

1

1

0

8

2

0

64

3

0

512

4

0

4,096

5

0

32,768

6

0

262,144

7

0

2,097,152

8

1

2,097,152

9

1

262,144

10

1

32,768

11

1

4,096

12

1

512

13

1

64

14

1

8

15

1

1

Recommended tDELAY

1µs to 16µs

8µs to 128µs

64µs to 1.024ms

512µs to 8.192ms

4.096ms to 65.54ms

32.77ms to 524.3ms

262.1ms to 4.194sec

2.097sec to 33.55sec

2.097sec to 33.55sec

262.1ms to 4.194sec

32.77ms to 524.3ms

4.096ms to 65.54ms

512µs to 8.192ms

64µs to 1.024ms

8µs to 128µs

1µs to 16µs

R1 (k)

Open

976

976

1000

1000

1000

1000

1000

887

681

523

392

280

182

102

Short

R2 (k)

Short

102

182

280

392

523

681

887

1000

1000

1000

1000

1000

976

976

Open

VDIV/V+

≤ 0.03125 ±0.015

0.09375 ±0.015

0.15625 ±0.015

0.21875 ±0.015

0.28125 ±0.015

0.34375 ±0.015

0.40625 ±0.015

0.46875 ±0.015

0.53125 ±0.015

0.59375 ±0.015

0.65625 ±0.015

0.71875 ±0.015

0.78125 ±0.015

0.84375 ±0.015

0.90625 ±0.015

≥ 0.96875 ±0.015

10000

1000

100

10

1

0.1

0.01

0

0.001

0V

POL BIT = 0

78

POL BIT = 1

6

9

5

10

4

11

3

12

2

13

1

14

0.5• V+

INCREASING VDIV

15

V+

699412 F02

Figure 2. Delay Range and POL Bit vs DIVCODE

For more information www.analog.com

Rev. C

13

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