WED9LAPC2C16V4BC View Datasheet(PDF) - White Electronic Designs => Micro Semi
Part Name
Description
MFG CO.
WED9LAPC2C16V4BC Datasheet PDF : 23 Pages
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WED9LAPC2C16V4BC
SSRAM OPERATION TRUTH TABLE
Operation
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
Address Used
CWE
COE
CDATA
External
L
X
D
External
H
L
Q
External
H
H
High-Z
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.
3. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z
time for SSOE and staying HIGH thoughout the input data hold time.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
FIG. 3 SSRAM READ TIMING
GCLK
CADDR
COE
CWE
CDATA
tKHKH tKHKL
tKLKH
tS
A1
A2
A3
A4
A5
tH
t OELQV
t OEHQZ
tKQLZ
tKHQX
tKHQV
Q(A1) Q(A2) Q(A3) Q(A4) Q(A5)
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
July 2000 Rev. 0
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