DS2181A View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
DS2181A Datasheet PDF : 32 Pages
| |||
DS2181A
Bits 4 through 8 of timeslot 0 in non-align frames are reserved for national use. When TCR.3 = 1, the
transmitted national bits are sourced from register locations TINR.4 through TINR.0. If TCR.3 = 0, the
national bits are sampled at TIND during bit times 4 through 8 of timeslot 0 in non-align frames.
Reserved bit positions in the TINR must be set to 0 when written; those bits can be 0 or 1 when read.
TXR: TRANSMIT EXTRA REGISTER Figure 10
(MSB)
(LSB)
-
-
-
-
XB1
TDMA
XB2
XB3
SYMBOL
-
-
-
-
XB1
TDMA
XB2
XB3
POSITION
TXR.7
TXR.6
TXR.5
TXR.4
TXR.3
TXR.2
TXR.1
TXR.0
NAME AND DESCRIPTION
Reserved; must be 0 for proper operation.
Reserved; must be 0 for proper operation.
Reserved; must be 0 for proper operation.
Reserved; must be 0 for proper operation.
Extra Bit 1
Transmit Distant Multiframe Alarm
0 = Normal operation; bit 6 of timeslot 16 in frame 0 clear.
1 = Alarm condition; bit 6 of timeslot 16 in frame 0 set.
Extra Bit 2
Extra Bit 3
TRANSMIT EXTRA DATA
In the CAS mode, timeslot 16 of frame 0 contains the multiframe alignment pattern, extra bits and the
distant multiframe alarm. When CAS is enabled (TCR.5 = 0), the extra bits are sourced from TXR.0,
TXR.1 and TXR.3 (TCR.2 = 1) or the extra bits are sampled externally at TXD during the extra bit time
(TCR.2 = 0). The extra bits, alignment pattern and alarm signal are not utilized in the CCS mode (TCR.5
= 1); input TSER overwrites all timeslot 16 bit positions.
Reserved bit positions in the TXR must be set to 0 when written; those bits can be 0 or 1 when read.
TIR1 - TIR4: TRANSMIT IDLE REGISTERS Figure 11
(MSB)
TS7
TS6
TS5
TS4
TS3
TS2
TS15 TS14 TS13
TS12
TS11
TS10
TS23 TS22 TS21
TS20
TS19
TS18
TS31 TS30 TS29
TS28
TS27
TS26
TS1
TS9
TS17
TS25
(LSB)
TS01
TS8
TS161
TS024
TIR1
TIR2
TIR3
TIR4
SYMBOL
TS31
TS0
POSITION
TIR4.7
TIR1.0
NAME AND DESCRIPTION
Transmit Idle Registers
Each of these bit positions represents a timeslot in the outgoing
stream at TPOS and TNEG; when set, the contents of that timeslot
are forced to idle code (11010101).
NOTE:
1. TS0 and TS16 are not affected by the idle register.
14 of 32
Share Link: 