HIP6304
RIN
FB
ERROR
AMPLIFIER
-
+
CORRECTION
∑
+-
HIP6304
COMPARATOR
-
PWM
+
CIRCUIT
PROGRAMMABLE
REFERENCE
+
∑
DAC
-
CURRENT
SENSING
I AVERAGE
-
∑+
CURRENT
AVERAGING
CURRENT
SENSING
-
+
∑
CORRECTION
COMPARATOR
+
PWM
-
CIRCUIT
VIN
PWM1
ISEN1
Q1
L01
HIP6601
Q2
IL1
PHASE
RISEN1
ISEN2
RISEN2
VIN
PHASE
PWM2
HIP6601
Q3
L02
IL2
Q4
VCORE
COUT RLOAD
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE HIP6304 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER
CHANNEL REGULATOR
Functional Pin Description
VID3 1
VID2 2
VID1 3
VID0 4
EN 5
COMP 6
FB 7
FS/DIS 8
16 VCC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3) and VID0
(Pin 4)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The HIP6304 decodes
VID bits to establish the output voltage. See Table 1.
EN (Pin 5)
Enable pin normal operation is with input open or high. A low
input disables the regulator and three states the PWM outputs.
COMP (Pin 6)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
FB (Pin 7)
Inverting input of the internal error amplifier.
4
FS/DIS (Pin 8)
Channel frequency, FSW, select and disable. A resistor from
this pin to ground sets the switching frequency of the
converter. Pulling this pin to ground disables the converter
and three states the PWM outputs. See Figure 10.
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
VSEN (Pin 10)
Power good monitor input. Connect to the microprocessor-
CORE voltage.
ISEN2 (Pin 11) and ISEN1 (Pin 14)
Current sense inputs from the individual converter channel’s
phase nodes.
PWM2 (Pin 12) and PWM1 (Pin 13)
PWM outputs for each driven channel in use. Connect these
pins to the PWM input of a HIP6601/2/3 driver.
PGOOD (Pin 15)
Power good. This pin provides a logic-high signal when the
microprocessor CORE voltage (VSEN pin) is within specified
limits and Soft-Start has timed out.
VCC (Pin 16)
Bias supply. Connect this pin to a 5V supply.