CY7C1425KV18 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C1425KV18 Datasheet PDF : 33 Pages
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CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
PLL
These chips use a PLL which is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time).
Application Example
Figure 2 shows two QDR II used in an application.
Figure 2. Application Example
SRAM #1
R = 250ohms
ZQ
Vt
RW B
D
PPW
SS S
CQ/CQ#
Q
R
A
# # # C C# K K#
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
Delayed K
Delayed K#
R
R = 50ohms Vt = Vddq/2
SRAM #2
ZQ R = 250ohms
RWB
P PW
D
SSS
CQ/CQ#
Q
A
# # # C C# K K#
Vt
Vt
R
Document Number: 001-57825 Rev. *I
Page 10 of 33
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