CY7C1021DV33-10BVXI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C1021DV33-10BVXI Datasheet PDF : 13 Pages
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CY7C1021DV33
Switching Characteristics Over the Operating Range[7]
Parameter
Read Cycle
tpower[8]
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU[11]
tPD[11]
tDBE
tLZBE
tHZBE
Write Cycle[12]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Description
VCC(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[10]
OE HIGH to High-Z[9, 10]
CE LOW to Low-Z[10]
CE HIGH to High-Z[9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z[10]
WE LOW to High-Z[9, 10]
Byte Enable to End of Write
-10 (Ind’l/Auto-A)
-12 (Auto-E)
Min.
Max.
Min.
Max.
Unit
100
100
s
10
12
ns
10
12
ns
3
3
ns
10
12
ns
5
6
ns
0
0
ns
5
6
ns
3
3
ns
5
6
ns
0
0
ns
10
12
ns
5
6
ns
0
0
ns
6
6
ns
10
12
ns
8
9
ns
8
9
ns
0
0
ns
0
0
ns
7
8
ns
5
6
ns
0
0
ns
3
3
ns
5
6
ns
7
8
ns
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. This parameter is guaranteed by design and is not tested.
12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the Write.
Document #: 38-05460 Rev. *F
Page 5 of 13
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