AD7298-1BCPZ-RL View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD7298-1BCPZ-RL

8-Channel, 1 MSPS, 10-Bit SAR ADC

Analog Devices 

CIRCUIT INFORMATION

The AD7298-1 is a high speed, 8-channel, 10-bit ADC. The part

can be operated from a 2.8 V to 3.6 V supply and is capable of

throughput rates of 1 MSPS per analog input channel.

The AD7298-1 provides the user with an on-chip, track-and-hold

ADC and a serial interface housed in a 20-lead LFCSP. The

AD7298-1 has eight, single-ended input channels with channel

repeat functionality, which allows the user to select a channel

sequence through which the ADC can cycle with each consecutive

CS falling edge. The serial clock input accesses data from the

part, controls the transfer of data written to the ADC, and

provides the clock source for the successive approximation

ADC. The analog input range for the AD7928-1 is 0 V to VREF.

The AD7298-1 operates with one cycle latency, which means

that the conversion result is available in the serial transfer

following the cycle in which the conversion is performed.

The AD7298-1 provides flexible power management options to

allow the user to achieve the best power performance for a given

throughput rate. These options are selected by programming

the partial power-down bit, PPD, in the control register and

using the PD/RST pin.

CONVERTER OPERATION

The AD7298-1 is a 10-bit successive approximation ADC based

around a capacitive DAC. Figure 19 and Figure 20 show simplified

schematics of the ADC. The ADC is comprised of control logic,

SAR, and a capacitive DAC that are used to add and subtract

fixed amounts of charge from the sampling capacitor to bring

the comparator back into a balanced condition. Figure 19 shows

the ADC during its acquisition phase. SW2 is closed and SW1 is

in Position A. The comparator is held in a balanced condition

and the sampling capacitor acquires the signal on the selected

VIN channel.

CAPACITIVE

DAC

VIN

GND1

A

SW1

B SW2

COMPARATOR

CONTROL

LOGIC

Figure 19. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 20), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the capacitive DAC are used to

add and subtract fixed amounts of charge to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC output code. Figure 22 shows the transfer

function of the ADC.

AD7298-1

CAPACITIVE

DAC

VIN

GND1

A

SW1

B SW2

CONTROL

LOGIC

COMPARATOR

Figure 20. ADC Conversion Phase

ANALOG INPUT

Figure 21 shows an equivalent circuit of the analog input structure

of the AD7298-1. The two diodes, D1 and D2, provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signal never exceeds the internally generated

LDO voltage of 2.5 V (DCAP) by more than 300 mV. This causes

the diodes to become forward-biased and to start conducting

current into the substrate. The maximum current these diodes

can conduct without causing irreversible damage to the part is

10 mA. Capacitor C1, in Figure 21, is typically about 8 pF and

can primarily be attributed to pin capacitance. The R1 resistor is

a lumped component made up of the on resistance of a switch

(track-and-hold switch) and includes the on resistance of the

input multiplexer. The total resistance is typically about 155 Ω.

The capacitor, C2, is the ADC sampling capacitor and has a

capacitance of 34 pF typically.

DCAP (2.5V)

D1

VIN

C2

R1 pF

C1

pF

D2

CONVERSION PHASE: SWITCH OPEN

TRACK PHASE: SWITCH CLOSED

Figure 21. Equivalent Analog Input Circuit

For ac applications, removing high frequency components from

the analog input signal is recommended by using an RC low-pass

filter on the relevant analog input pin. In applications where

harmonic distortion and signal-to-noise ratios are critical, the

analog input should be driven from a low impedance source. Large

source impedances significantly affect the ac performance of the

ADC. This may necessitate the use of an input buffer amplifier.

The choice of the op amp is a function of the particular application

performance criteria.

Rev. A | Page 13 of 24

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