ISL6556ACR-T View Datasheet(PDF) - Renesas Electronics

Part Name

Description

MFG CO.

ISL6556ACR-T

Optimized Multiphase PWM Controller with 6-Bit DAC for VR10.X Application

Renesas Electronics 

ISL6556A

use an input capacitor bank with twice the RMS current

capacity as the equivalent three-phase converter.

INPUT-CAPACITOR CURRENT, 10A/DIV

CHhaAnNnNeEl 3L 3

iINnpPuUtTcCurUreRnRtENT

10A/DIV

CHANNEL 2

INPUT CURRENT

10A/DIV

CHANNEL 1

INPUT CURRENT

10A/DIV

1s/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

Figures 14, 15 and 16 in the section entitled Input Capacitor

Selection can be used to determine the input-capacitor RMS

current based on load current, duty cycle, and the number of

channels. They are provided as aids in determining the optimal

input capacitor solution. Figure 17 shows the single phase

input-capacitor RMS current for comparison.

PWM Operation

The timing of each converter leg is set by the number of active

channels. The default channel setting for the ISL6556A is four.

One switching cycle is defined as the time between PWM1

pulse termination signals. The pulse termination signal is the

internally generated clock signal that triggers the falling edge

of PWM1. The cycle time of the pulse termination signal is the

inverse of the switching frequency set by the resistor between

the FS pin and ground. Each cycle begins when the clock

signal commands the channel-1 PWM output to go low. The

PWM1 transition signals the channel-1 MOSFET driver to turn

off the channel-1 upper MOSFET and turn on the channel-1

synchronous MOSFET. In the default channel configuration,

the PWM2 pulse terminates 1/4 of a cycle after PWM1. The

PWM3 output follows another 1/4 of a cycle after PWM2.

PWM4 terminates another 1/4 of a cycle after PWM3.

If PWM3 is connected to VCC, two channel operation is

selected and the PWM2 pulse terminates 1/2 of a cycle later.

Connecting PWM4 to VCC selects three channel operation

and the pulse-termination times are spaced in 1/3 cycle

increments.

Once a PWM signal transitions low, it is held low for a minimum

of 1/3 cycle. This forced off time is required to ensure an

accurate current sample. Current sensing is described in the

next section. After the forced off time expires, the PWM output

is enabled. The PWM output state is driven by the position of

the error amplifier output signal, VCOMP, minus the current

correction signal relative to the sawtooth ramp as illustrated in

Figure 4. When the modified VCOMP voltage crosses the

sawtooth ramp, the PWM output transitions high. The

MOSFET driver detects the change in state of the PWM signal,

turns off the synchronous MOSFET and turns on the upper

MOSFET. The PWM signal remains high until the pulse

termination signal commands the beginning of the next cycle

by triggering the PWM signal low.

Current Sensing

During the forced off time following a PWM transition low, the

controller senses channel current by sampling the voltage

across the lower MOSFET rDS(ON) (see Figure 3). A ground-

referenced operational amplifier, internal to the ISL6556A, is

connected to the PHASE node through a resistor, RISEN. The

voltage across RISEN is equivalent to the voltage drop across

the rDS(ON) of the lower MOSFET while it is conducting. The

resulting current into the ISEN pin is proportional to the channel

current, IL. The ISEN current is sampled and held after sufficient

settling time every switching cycle. The sampled current, In, is

used for channel-current balance, load-line regulation,

overcurrent protection, and module current sharing. From Figure

3, the following equation for In is derived

In = IL r---DR----SI--S----OE----NN-----

(EQ. 3)

where IL is the channel current.

If rDS(ON) sensing is not desired, an independent current-

sense resistor in series with the lower MOSFET source can

serve as a sense element. The circuitry shown in Figure 3

represents channel n of an N-channel converter. This circuitry

is repeated for each channel in the converter, but may not be

active depending upon the status of the PWM3 and PWM4

pins as described under PWM Operation section.

In

ISEN = IL -r--D-R----SI--S-----OE----N-N-----

SAMPLE

&

HOLD

-

+

VIN

CHANNEL N

UPPER MOSFET

IL

ISEN(n)

RISEN

-

IL rDSON

+

CHANNEL N

LOWER MOSFET

ISL6556A INTERNAL CIRCUIT EXTERNAL CIRCUIT

FIGURE 3. INTERNAL AND EXTERNAL CURRENT-SENSING

CIRCUITRY

FN9096 Rev 3.00

December 29, 2004

Page 11 of 24

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