ISL6531 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
MFG CO.
ISL6531 Datasheet PDF : 18 Pages
| |||
ISL6531
While the VTT supply “floats”, it is held to about 50% of VDDQ
via a low current window regulator which drives VTT via the
SENSE2 pin. The window regulator can overcome up to at
least 10mA of leakage on VTT.
While V2_SD is high, PGOOD is low.
PHASE1 and PHASE2
Connect PHASE1 and PHASE2 to the corresponding upper
MOSFET source. This pin is used as part of the upper
MOSFET bootstrapped drives. PHASE1 is used to monitor the
voltage drop across the upper MOSFET of the VDDQ regulator
for overcurrent protection. The PHASE1 pin is monitored by
the adaptive shoot through protection circuitry to determine
when the upper FET of the VDDQ supply has turned off.
FB1, COMP1
COMP1 and FB1 are the available external pins of the error
amplifier for the VDDQ regulator. The FB1 pin is the inverting
inputs of the error amplifier and the COMP1 pin is the
associated output. An appropriate AC network across these
pins is used to compensate the voltage-controlled feedback
loop of the VDDQ converter.
VREF and VREF_IN
VREF produces a voltage equal to one half of the voltage on
SENSE1. This low current output is connected to the VREF
input of the DDRAM devices being powered. This same
voltage is used as the reference input of the VTT error
amplifier. Thus VTT is controlled to 50% of VDDQ.
VREF_IN is used as an option to overdrive the internal resistor
divider network that sets the voltage for both VREF_OUT and
the reference voltage for the VTT supply. A 100pF capacitor
between VREF_IN and ground is recommended for proper
operation.
PVCC1
This is the positive supply for the lower gate driver, LGATE1.
PVCC1 is connected to a well decoupled 5V.
SENSE1 and SENSE2
Both SENSE1 and SENSE2 are connected directly to the
regulated outputs of the VDDQ and VTT supplies, respectively.
SENSE1 is used as an input to create the voltage at
VREF_OUT and the reference voltage for the VTT supply.
SENSE2 is used as the feedback pin of the VTT regulator and
as the regulation point for the window regulator that is enabled
in V2_SD mode.
Functional Description
Overview
The ISL6531 contains control and drive circuitry for two
synchronous buck PWM voltage regulators. Both regulators
utilize 5V bootstrapped output topology to allow use of low cost
N-Channel MOSFETs. The regulators are driven by 300kHz
clocks. The clocks are phase locked and displaced 90o to
minimize noise coupling between the controllers.
The first regulator includes a precision 0.8V reference and is
intended to provide the proper VDDQ to a DDRAM memory
system. The VDDQ controller implements overcurrent
protection utilizing the rDS(ON) of the upper MOSFET.
Following a fault condition, the VDDQ regulator is softstarted
via a digital soft-start circuit.
Included in the ISL6531 is a precision VREF reference output.
VREF is a buffered representation of
1--
2
VDDQ
.
VREF
is
derived via a precision internal resistor divider connected to
the SENSE1 terminal.
The second PWM regulator is designed to provide VTT
termination for the DDRAM signal lines. The reference to the
VTT regulator is VREF. Thus the VTT regulator provides a
termination voltage equal to
1--
2
VDDQ
.
The
drain
of
the
upper
MOSFET of the VTT supply is connected to the regulated
VDDQ voltage. The VTT controller is designed to enable both
sinking and sourcing current on the VTT rail.
Two benefits result from the ISL6531 dual controller topology.
First, as VREF is always
1--
2
VDDQ
,
the
VTT
supply
will
track
the VDDQ supply during soft-start cycles. Second, the
overcurrent protection incorporated into the VDDQ supply will
simultaneously protect the VTT supply.
Initialization
The ISL6531 automatically initializes upon application of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage at the VCC pin. The
POR function initiates soft-start operation after the 5V bias
supply voltage exceeds its POR threshold.
Soft-Start
The POR function initiates the digital soft start sequence. The
PWM error amplifier reference input for the VDDQ regulator is
clamped to a level proportional to the soft-start voltage. As the
soft-start voltage slews up, the PWM comparator generates
PHASE pulses of increasing width that charge the output
capacitor(s). This method provides a rapid and controlled output
voltage rise. The soft-start sequence typically takes about 7ms.
With the VTT regulator reference held at
1--
2
VDDQ
it
will
automatically track the ramp of the VDDQ softstart, thus
enabling a soft-start for VTT.
Figure 2 shows the soft-start sequence for a typical application. At
T0, the +5V VCC bias voltage starts to ramp. Once the voltage on
VCC crosses the POR threshold at time T1, both outputs begin
their soft-start sequence. The triangle waveforms from the PWM
oscillators are compared to the rising error amplifier output
voltage. As the error amplifier voltage increases, the pulse-widths
on the UGATE pins increase to reach their steady-state duty cycle
at time t2.
FN9053 Rev 2.00
Aug 11, 2005
Page 7 of 18
Share Link: 