DS26334 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

MFG CO.

DS26334

3.3V, 16-Channel, E1/T1/J1 Short- and Long-Haul Line Interface Unit

Maxim Integrated 

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 5-3. Serial Port Operation for Read Access with CLKE = 1

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CSB

SDI

0

A1

A2

A3

A4

A5

SDO

(lsb)

A6

X

(msb)

D0

D1

D2

D3

D4

D5

D6

D7

(lsb)

(msb)

5.1.2 Parallel Port Operation

When using the parallel interface on the DS26334 the user has the option for either multiplexed bus operation or

nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26334 can

operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects

the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following Table lists all the

pins and their functions in the parallel port mode. See the timing diagrams in Section 9 for more details.

Table 5-1. Parallel Port Mode Selection and Pin Functions

MODESEL, MOTEL,

MUX

100

110

101

111

PARALLEL HOST

INTERFACE

Nonmultiplexed Motorola

Nonmultiplexed Intel

Multiplexed Motorola

Multiplexed Intel

ADDRESS, DATA, AND CONTROL

CSB, ACKB, DSB, RWB, ASB, A[5:0], D[7:0], INTB

CSB, RDYB, WRB, RDB, ALE, A [5:0], D[7:0], INTB

CSB, ACKB, DSB, RWB, ASB, AD[7:0], INTB

CSB, RDYB, WRB, RDB, ALE, AD[7:0], INTB

5.1.3 Interrupt Handling

There are four sets of events that can potentially trigger an Interrupt. The interrupt functions as follows:

• When status changes on an interruptible event, INTB pin will go low if the event is enabled through the

corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10kΩ resister for

wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when

not active by setting register GISC.INTM.

• When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source

of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The

Interrupt Status register can also be configured as clear on write as per register GISC.CWE. When set to clear

on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a ‘1’ to

it’s bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a

register without clearing them on all bits.

• Subsequently the host processor can read the corresponding Status Register to check the real-time status of

the event.

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