DS2760BE View Datasheet(PDF) - Maxim Integrated

Part Name

Description

MFG CO.

DS2760BE

High-Precision Li+ Battery Monitor

Maxim Integrated 

DS2760

I/O SIGNALING

The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the

DS2760 are: the initialization sequence (Reset Pulse followed by Presence Pulse), Write 0, Write 1, and

Read Data. All of these types of signaling except the Presence Pulse are initiated by the bus master.

The initialization sequence required to begin any communication with the DS2760 is shown in Figure 17.

A Presence Pulse following a Reset Pulse indicates the DS2760 is read to accept a Net Address

Command. The bus master transmits (Tx) a Reset Pulse for tRSTL. The bus master then releases the line

and goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pull-up resistor. After

detecting the rising edge on the DQ pin, the DS2760 waits for tPDH and then transmits the Presence Pulse

for tPDL.

1-WIRE INITIALIZATION SEQUENCE Figure 17

tRSTL

tPDH

DQ

LINE TYPE LEGEND:

Bus master active low

Both bus master and

DS2760 active low

tPDL

tRSTH

DS2760 active low

Resistor pullup

PACK+

PACK–

WRITE TIME SLOTS

A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic high (inactive) level to

a logic low level. There are two types of write time slots: Write 1 and Write 0. All write time slots must

be tSLOT (60ms to 120ms) in duration with a 1ms minimum recovery time, tREC, between cycles. The

DS2760 samples the 1-Wire bus line between 15ms and 60ms after the line falls. If the line is high when

sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 18). For the bus

master to generate a Write 1 time slot, the bus line must be pulled low and then released, allowing the line

to be pulled high within 15ms after the start of the write time slot. For the host to generate a Write 0 time

slot, the bus line must be pulled low and held low for the duration of the write time slot.

READ TIME SLOTS

A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to a

logic low level. The bus master must keep the bus line low for at least 1ms and then release it to allow the

DS2760 to present valid data. The bus master can then sample the data tRDV (15ms) from the start of the

read time slot. By the end of the read time slot, the DS2760 releases the bus line and allows it to be

pulled high by the external pull-up resistor. All read time slots must be tSLOT (60ms to 120ms) in duration

with a 1ms minimum recovery time, tREC, between cycles. See Figure 18 for more information.

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