AK8130AH View Datasheet(PDF) - Asahi Kasei Microdevices
Part Name
Description
MFG CO.
AK8130AH Datasheet PDF : 8 Pages
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AK8130AH
Typical Connection Diagram
+3.3V typ.
27.0MHz AT Cut Crystal
MPEG-TS
DECODER
Cext1
Cext2
AK8130AH
CTL OUT2
CTL OUT0
1:X1
X2:16
C3
2:S0
VDD3:15
CTL OUT1
DC Voltage
CTL OUT
(PWM)
R11
C11
C1
3:S1
4:VIN
5:VDD1
6:GND1
7:CLK1
S2:14
VDD2:13
GND2:12
CLK4:11
CLK3:10
C2
IEEE1394
24.576MHz
USB I/F
12.0/48.0MHz
REF CLK IN
8:CLK2
1
2
REFOUT:9
Ethernet I/F
25.0MHz
3
HD Display I/F
4
GND
5
74.25/74.1758MHz
6
Figure 2: Typic7al Connection Diagram
8
C1, C2, C3: 0.1F
Cext1, Cext2: Depends on crystal characteristics. Refer the specification of the crystal.
R11, C11: In case of interface by PWM. For right configuration, refer the specification of the
applied processor.
PCB Layout Consideration
The AK8130AH is a high-accuracy and low-jitter multi clock generator. For proper performances specified
in this datasheet, careful PCB layout should be taken. The followings are layout guidelines based on the
typical connection diagram shown in Figure 2
Power supply line – AK8130AH has three power supply pins (VDD1-3) which deliver power to internal
circuitry segments. A 0.1F decoupling capacitor should be placed as close to each VDD pin as possible.
Ground pin connection – AK8130AH has two ground pins (GND1-2). These pin require connecting to
plane ground which will eliminate any common impedance with other critical switching signal return.
0.1F decoupling capacitors placed at VDD1, VDD2, and VDD3 should be grounded at close to the
GND1pin, the GND2 pin, and the GND2, respectively.
Crystal connection – Proper oscillation performance and pullable range are susceptible to stray or
parasitic capacitors around crystal. The wiring traces to a crystal form X1 (Pin 1) and X2 (Pin 14) have
equal lengths with no via and as short in length as possible. These traces should be also located away
from any traces with switching signal.
Dec-2013
MS0631-E-03
-6-
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