SNAD02C
8-CHANNEL 10-BIT ADC
6. Functional Descriptions
VDD
Host CPU
Output Port1
Output Port2
I/O port
START
CLK
DIO
SNAD02
VDD
START
AVDD
CLK
REF
DIO
VSS
AVSS
0.1uF
CH[0]
CH[1]
CH[7]
Analog/Digital
Signal
Figure-2 Interface with Host CPU
6.1. Interface Format
START
CLK
Channel Setting
HiZ
DIO
CM2 CM1 CM0 CH[7] CH[6] CH[5] CH[4] CH[3] CH[2] CH[1] CH[0] X
X
X
X
X
Port Input
Control Register Setting
HiZ
DIO
CM2 CM1 CM0
PH PL RF MB
X
X
X
X
X
X
X
X
X
Port Input
Digital Input Reading
HiZ
DIO
CM2
CM1 CM0
DI[7] DI[6] DI[5] DI[4] DI[3] DI[2] DI[1] DI[0] DI[7] DI[6] DI[5] DI[4] DI[3]
Port Input
Port Output
Power Down
HiZ
DIO
CM2 CM1 CM0
PDS PDS PDS PDS PDS PDS PDS PDS PDS PDS PDS PDS PDS
Port Input
Port Output
Figure-3 Timing Diagram of Whole Commands
Version: 1.3
5
July 31, 2003