OX16PCI952 View Datasheet(PDF) - Oxford Semiconductor
Part Name
Description
MFG CO.
OX16PCI952
Oxford Semiconductor
OX16PCI952 Datasheet PDF : 77 Pages
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OXFORD SEMICONDUCTOR LTD.
OX16PCI952
7 INTERNAL OX16C950 UART
Each of the internal UARTs in the OX16PCI952 is an OX16C950 rev B specification high-performance serial port. The features
of this UART are described in this section.
7.1 Operation – mode selection
The UART is backward compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs. The operation of the port depends
on a number of mode settings, which are referred to throughout this section. The modes, conditions and corresponding FIFO
depth are tabulated below:
UART Mode FIFO
size
450
1
550
16
Extended 550 128
650
128
750
128
9501
128
FCR[0]
0
1
1
1
1
1
Enhanced mode
(EFR[4]=1)
X
0
0
1
0
1
FCR[5]
(guarded with LCR[7] = 1)
X
0
X
X
1
X
FIFOSEL
Pin
X
0
1
X
0
X
Table 8: UART Mode Configuration
Note 1: 950 mode configuration is identical to 650 configuration
7.1.1 450 Mode
After a hardware reset, bit 0 of the FIFO Control Register
(‘FCR’) is cleared, hence the UART is compatible with the
16C450. The transmitter and receiver FIFOs (referred to as
the ‘Transmit Holding Register’ and ‘Receiver Holding
Register’ respectively) have a depth of one. This is referred
to as ‘Byte mode’. When FCR[0] is cleared, all other mode
selection parameters are ignored.
7.1.2 550 Mode
After a hardware reset, writing a 1 to FCR[0] will increase
the FIFO size to 16, providing compatibility with 16C550
devices.
7.1.3 750 Mode
Writing a 1 to FCR[0] will increase the FIFO size to 16. In a
similar fashion to 16C750, the FIFO size can be further
increased to 128 by writing a 1 to FCR[5]. Note that access
to FCR[5] is protected by LCR[7]. i.e., to set FCR[5],
software should first set LCR[7] to temporarily remove the
guard. Once FCR[5] is set, the software should clear
LCR[7] for normal operation.
The 16C750 additional features are available as long as
the UART is not put into Enhanced mode; i.e. ensure
EFR[4] = ‘0’. These features are:
• Sleep mode
7.1.4 650 Mode
The OX16PCI952 UART is compatible with the 16C650
when EFR[4] is set, i.e. the device is in Enhanced mode.
As 650 software drivers usually put the device in Enhanced
mode, running 650 drivers on the one of the UART
channels will result in 650 compatibility with 128 deep
FIFOs, as long as FCR[0] is set. Note that the 650
emulation mode of the OX16PCI952 provides 128-deep
FIFOs rather than the 32 provided by a legacy 16C650.
In enhanced (650) mode the device has the following
features available over those provided by a generic 550.
(Note: some of these are similar to those provided in 750
mode, but enabled using different registers).
• Deeper FIFOs
• Sleep mode
• Automatic in-band flow control
• Special character detection
• Infra-red “IrDA-format” transmit and receive mode
• Transmit trigger levels
• Optional clock prescaler
• Deeper FIFOs
• Automatic RTS/CTS out-of-band flow control
DS-0028 Jul 05
External-Free Release
Page 29
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