OX16PCI952 View Datasheet(PDF) - Oxford Semiconductor
Part Name
Description
MFG CO.
OX16PCI952
Oxford Semiconductor
OX16PCI952 Datasheet PDF : 77 Pages
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OXFORD SEMICONDUCTOR LTD.
OX16PCI952
Bits Description
Read/Write
EEPROM PCI
29
Reload configuration from EEPROM.
-
W
Writing a 1 to this bit re-loads the configuration from EEPROM. This bit is
self-clearing after an EEPROM read
30
Reserved
-
-
31
Reserved
-
R
Reset
0
0
0
6.4.2 Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
This register configures the operation of the multi-purpose I/O pins ‘MIO[1:0]’ as follows.
Bits
Description
1:0
MIO0 Configuration Register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
Read/Write
EEPROM
PCI
W
RW
3:2
MIO1 Configuration Register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
W
RW
4
MIO0 Power Management Event (PME) Enable.
W
RW
A value of ‘1’ enables the MIO0 pin to set the PME_Status bit in the
Power Management Register PMCSR of the selected function, and
hence assert the PME# pin if this option has been enabled. A value of ‘0’
prevents MIO0 from setting the PCI PME_Status bit.
This pin can affect function 0 or function 1, through the control defined in
the GIS (local configuration) register.
5
MIO1 Power Management Event (PME) Enable.
W
RW
A value of ‘1’ enables the MIO1 pin to set the PME_Status bit in the
Power Management Register PMCSR of the selected function, and
hence assert the PME# pin if this option has been enabled. A value of ‘0’
prevents MIO1 from setting the PCI PME_Status bit.
This pin can affect function 0 or function 1, through the control defined in
the GIS (local configuration) register.
31:6
Reserved
-
R
Reset
00
00
0
0
0000h
DS-0028 Jul 05
External-Free Release
Page 21
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