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OX16PCI952 View Datasheet(PDF) - Oxford Semiconductor

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Description
MFG CO.
OX16PCI952 Datasheet PDF : 77 Pages
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OXFORD SEMICONDUCTOR LTD.
OX16PCI952
6.2 Configuration space
The OX16PCI952 is a dual-function (or single function)
device, where each logical function has its own PCI
configuration space.
All the required fields in the predefined PCI header region
have been implemented. The device dependant region of
the PCI configuration space contains the PCI Power
Management Extended Capability register set.
The format of the configuration space, for both function 0
and function 1, is as shown in Table 4, below.
In general, writes to any registers that are not implemented
are ignored, and all reads from unimplemented registers
return 0.
6.2.1 PCI Configuration Space Register map
Configuration Register Description
31
16
15
0
Device ID
Vendor ID
Status
Command
Class Code
Revision ID
BIST1
Header Type
Reserved
Reserved
Base Address Register 0 (BAR 0)
Function 0 – UART0 in I/O Space
Function 1 – Parallel Port Base Register Set in I/O Space
Base Address Register 1 (BAR 1)
Function 0 – UART1 I/O Space
Function 1 – Parallel Port Extended Register Set in I/O space
Base Address Register 2 (BAR 2)
Local Configuration Registers in IO space, for function 0 and function 1
Base Address Register 3 (BAR 3)
Local Configuration Registers in Memory space, for function 0 and function 1
Base Address Register 4 (BAR 4)
Function 0 – UART0 and UART1 in Memory Space
Function 1 – Not Implemented.
Base Address Register 5 (BAR5)
Not Implemented, for function 0 and function 1
Reserved
Subsystem ID
Subsystem Vendor ID
Reserved
Reserved
Cap_Ptr
Reserved
Reserved
Reserved
Interrupt Pin
Interrupt Line
Predefined PCI Header Region
Device Dependent PCI Region
Power Management Capabilities (PMC)
Reserved
Reserved
Next Ptr
Cap_ID
PMC Control/Status Register (PMCSR)
Table 4: PCI Configuration space (for UART and Parallel Port function)
Offset
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
DS-0028 Jul 05
External-Free Release
Page 16

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