MGA-86563 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
MGA-86563 Datasheet PDF : 8 Pages
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RF Layout
The RF layout in Figure 13 is suggested as a starting point for
amplifier designs using the MGA-86563 MMIC. Adequate
grounding is needed to obtain maximum performance
and to obviate potential instability. All four ground pins
of the MMIC should be connected to RF ground by using
plated through holes (vias) near the package terminals.
It is recommended that the PCB pads for the ground pins
NOT be connected together underneath the body of the
package. PCB traces hidden under the package cannot be
adequately inspected for SMT solder quality.
50 Ω
RF INPUT
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50 Ω
RF OUTPUT
AND Vd
Figure 13. RF Layout.
PCB Material
FR-4 or G-10 printed circuit board material is a good
choice for most low cost wireless applications. Typical
board thickness is 0.020 or 0.031 inches. The width of 50Ω
microstriplines in PC boards of these thicknesses is also
convenient for mounting chip components such as the
series inductor that is used at the input for impedance
matching or for DC blocking capacitors.
For applications requiring the lowest noise figures, the
use of PTFE/glass dielectric materials may be warranted
to minimize transmission line losses at the amplifier input.
A 0.5 inch length of 50Ω microstripline on FR-4 has ap-
proximately 0.3 dB loss at 4 GHz which will add directly
to the noise figure of the MGA-86563.
Typical Application Circuit
A typical implementation of the MGA-86563 as a low noise
amplifier is shown in Figure 14.
A 50Ω microstripline with a series DC blocking capacitor,
C1, is used to feed RF to the MMIC. The input of the MGA-
86563 is already partially matched for noise figure and gain
to 50Ω. The use of a simple input matching circuit, such as
a series inductor, will minimize amplifier noise figure. Since
the impedance match for NF (minimum noise figure) is
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very close to a conjugate power match, a low noise figure
can be realized simultaneously with a low input VSWR.
DC power is applied to the MMIC through the same pin
that is shared with the RF output. A 50Ω microstripline is
used to connect the device to the following stage. A bias
decoupling network is used to feed in V while simultan-
d
eously providing a DC block to the RF signal. The bias de-
coupling network shown in Figure 14, consisting of resistor
R1, a short length of high impedance microstripline, and
bypass capacitor C3, will provide excellent performance
over a wide frequency range. Surface mount chip inductors
could be used in place of the high impedance transmission
line to act as an RF choke. Consideration should be given
to potential resonances and signal radiation when using
lumped inductors.
For operation at frequencies below approximately 2 GHz,
the addition of a simple impedance matching circuit to
the output will increase the gain and output power by
0.5 to 1.5 dB. The output matching circuit will not effect
the noise figure.
A small value resistor placed in series with the V line
dd
may be useful to “de-Q” the bias circuit. Typical values
of R1 are in the 10 Ω to 100 Ω range. Depending on the
value of resistance used, the supply voltage may have to
be increased to compensate for voltage drop across R1.
The power supply should be capacitively bypassed (C3)
to ground to prevent undesirable gain variations and to
eliminate unwanted feedback through the bias lines that
could cause oscillation.
Vd
C3
HIGH Z
R1
C1
L1
50 Ω
50 Ω
C2
50 Ω
50 Ω
Figure 14. Typical Amplifier Circuit.
Higher Bias Voltages
While the MGA-86563 is designed primarily for use in +5
volt applications, the internal bias regulation circuitry
allows it to be operated with any power supply voltage
from +5 to +7 volts. The use of +7 volts increases the P1dB
by approximately 1 dBm. The effect on noise figure, gain,
and VSWR with higher V is negligible.
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For more information call your nearest Avago sales of-
fice.
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