FW802A-DB View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

MFG CO.

FW802A-DB

Low-Power PHY IEEE* 1394A-2000 Two-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

FW802A Low-Power PHY IEEE 1394A-2000

Two-Cable Transceiver/Arbiter Device

Data Sheet, Rev. 3

June 2001

Internal Register Configuration

The PHY register map is shown below in Table 8.

Table 8. PHY Register Map for the Cable Environment

Address

00002

00012

00102

00112

01002

01012

01102

01112

10002

Contents

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Physical_ID

R

PS

RHB

IBR

Gap_count

Extended (7)

Max_speed

XXXXX

XXXXX

Total_ports

Delay

LCtrl Contender

Jitter

Pwr_class

Resume_int ISBR

Loop Pwr_fail Timeout Port_event Enab_accel Enab_multi

XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

Page_select

XXXXX

Port_select

Register 0 Page_select

11112

Register 7 Page_select

REQUIRED

XXXXX

RESERVED

The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values

not specified are resolved by the operation of the PHY state machines subsequent to a power reset.

Table 9. PHY Register Fields for the Cable Environment

Field Size Type

Physical_ID 6

r

R

PS

RHB

1

r

1

r

1 rw

IBR

1 rw

Gap_count 6 rw

Extended 3

r

18

Power Reset

Value

000000

0

—

0

0

3F16

7

Description

The address of this node determined during self-identification. A

value of 63 indicates a malconfigured bus; the link will not transmit

any packets.

When set to one, indicates that this node is the root.

Cable power active.

Root hold-off bit. When set to one, the force_root variable is TRUE,

which instructs the PHY to attempt to become the root during the

next tree identify process.

Initiate bus reset. When set to one, instructs the PHY to set ibr

TRUE and reset_time to RESET_TIME. These values in turn

cause the PHY to initiate a bus reset without arbitration; the reset

signal is asserted for 166 µs. This bit is self-clearing.

Used to configure the arbitration timer setting in order to optimize

gap times according to the topology of the bus. See Section 4.3.6

of IEEE Standard 1394-1995 for the encoding of this field.

This field has a constant value of seven, which indicates the

extended PHY register map.

Agere Systems Inc.

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