74ALVCH16501(2019) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
74ALVCH16501 Datasheet PDF : 15 Pages
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Nexperia
74ALVCH16501
18-bit universal bus transceiver; 3-state
10.1. Waveforms and test circuit
Fig. 6.
VI
An, Bn
input
VM
VM
GND
VOH
Bn, An
output
tPHL
VM
tPLH
VM
VOL
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Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Propagation delay, data input (An, Bn) to data output (Bn, An)
Fig. 7.
VI
OEAB, OEBA
input
GND
VCC
An, Bn output
LOW-to-OFF
OFF-to-LOW
VOL
VOH
An, Bn output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
tPLZ
tPHZ
VX
VY
outputs
enabled
VM
tPZL
tPZH
outputs
disabled
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
3-state output enable and disable times
VM
VM
outputs
enabled
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Fig. 8.
1 / fmax
LExx VI
input
CPxx
input GND
VOH
An, Bn
output
VOL
VM
VM
tW
tPHL
VM
VM
tPLH
VM
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Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output,
and pulse width
74ALVCH16501
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 13 March 2019
© Nexperia B.V. 2019. All rights reserved
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