SAB-C513A-2RN View Datasheet(PDF) - Infineon Technologies
Part Name
Description
MFG CO.
SAB-C513A-2RN Datasheet PDF : 43 Pages
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C511 / C513
CPU
The C511/C513 are efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and for bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % three-
byte instructions. With a 12 MHz crystal, 58 % of the instructions execute in 1 µs.
Special Function Register PSW (Address D0H)
MSB
Bit No. 7
6
D0H CY AC
5
4
3
2
F0 RS1 RS0 OV
Reset Value : 00H
LSB
1
0
F1
P
PSW
Bit
CY
AC
F0
RS1 RS0
00
01
10
11
OV
F1
P
Function
Carry Flag
Auxiliary Carry Flag (for BCD operations)
General Purpose Flag
Register Bank select control bits
Bank 0 selected, data address 00H-07H
Bank 1 selected, data address 08H-0FH
Bank 2 selected, data address 10H-17H
Bank 3 selected, data address 18H-1FH
Overflow Flag
General Purpose Flag
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/even number of
"one" bits in the accumulator, i.e. even parity.
Semiconductor Group
16
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