IDT79R304125 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

IDT79R304125

INTEGRATED RISController™ FOR LOW-COST SYSTEMS

Integrated Device Technology 

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

System Control Co-Processor

The R3041 also integrates on-chip a System Control Co-

processor, CP0. CP0 manages the exception handling capa-

bility of the R3041, the virtual to physical address mapping of

the R3041, and the programmable bus interface capabilities

of the R3041. These topics are discussed in subsequent

sections.

The R3041 does not include the optional TLB found in other

members of the RISController family, but instead performs the

same virtual to physical address mapping of the base version

of the RISController family. These devices still support

distinct kernel and user mode operation, but do not require

page management software or an on-chip TLB, leading to a

simpler software model and a lower-cost processor.

The memory mapping used by these devices is illustrated

in Figure 3. Note that the reserved address spaces shown are

for compatibility with future family members; in the current

family members, references to these addresses are trans-

lated in the same fashion as their respective segments, with

no traps or exceptions taken.

When using the base versions of the architecture, the

system designer can implement a distinction between the

user tasks and the kernel tasks, without having to execute

page management software. This distinction can take the

form of physical memory protection, accomplished by ad-

dress decoding, or in other system specific forms. In systems

which do not wish to implement memory protection, and wish

to have the kernel and user tasks operate out of a single

unified memory space, upper address lines can be ignored by

the address decoder, and thus all references will be seen in

the lower gigabyte of the physical address space.

The R3041 adds additional resources into the on-chip CP0.

These resources are detailed in the R3041 User's Manual.

They allow kernel software to directly control activity of the

processor internal resources and bus interface, and include:

• Cache Configuration Register: This register controls the

data cache block size and miss refill algorithm.

• Bus Control Register: This register controls the behavior

of the various bus interface signals.

• Count and Compare Registers: Together, these two

registers implement a programmable 24-bit timer, which

can be used for DRAM refresh or as a general purpose

timer.

• Port Size Control Register: This register allows the kernel

to indicate the port width of reads and writes to various sub-

regions of the physical address space. Thus, the R3041 can

interface directly with 8-, 16-, and 32-bit memory ports,

including a mix of sizes, for both instruction and data

references, without requiring additional external logic.

0xffffffff

0xfff00000

0xffefffff

0xc0000000

0xbfffffff

0xa0000000

0x9fffffff

0x80000000

0x7fffffff

0x7ff00000

0x7fefffff

VIRTUAL

Kernel Reserved

1MB

Kernel Cached

(kseg2)

Kernel Uncached

(kseg1)

Kernel Cached

(kseg0)

User Reserved

1MB

PHYSICAL

Kernel Reserved

1MB

Kernel Cached

Tasks

1023 MB

User Reserved

1MB

Kernel/User

Cached

Tasks

2047 MB

0xffffffff

0xfff00000

0xffefffff

0xc0000000

0xbfffffff

0xbff00000

0xbfefffff

0x00000000

Kernel/User

Cached

(kuseg)

Inaccessible

512 MB

Kernel Boot

and I/O

512 MB

Figure 3. Virtual to Physical Mapping of Base Architecture Versions

0x40000000

0x3fffffff

0x20000000

0x1fffffff

0x00000000

2905 drw 03

3

Share Link: