CMPWR025 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
CMPWR025 Datasheet PDF : 8 Pages
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CMPWR025
Typical Transient Characteristics
The circuit schematic in Figure 6 below shows the
transient characterization test setup. It includes the power
supply source impedances RS1 and RS2, which represent the
power supplies’ output impedances and interconnection
parasitics to the VCC1 and VCC2 input pins. In this test
set−up, the series resistances on VCC1 and VCC2 are
respectively RS1 = 0.16 W, and RS2 = 0.06 W, unless
specified otherwise. A load resistance RL of 11 W is used,
setting a load current of about 450 mA at 5 V.
The hysteresis level is increased by connecting pin 8 to
ground, which will improve the transient performance in
noisy environments. In the transient analysis, the rise time
and fall time of VCC1 is very long, in the 20 msec range,
providing a worst case situation.
Important note: The power supply source impedance
must be as low as possible to avoid chatter during power
transition. When operating in a high load and long rise time
power−up condition, we recommend not exceeding a value
of 0.15 W on both source resistances.
VHYS u I (RS ) RT)
Where: VHYS = The Minimum Hysteresis
Voltage = 80 mV
RS = The Power Supply Output Impedance
RT = The PCB Trace Impedance
For a rated load of 600 mA, RS + RT < 0.15 W.
RS1
VCC1
5V
TR=20ms
TF=20ms
C1 + C2
0.1 mF 10 mF
GND
RS2
+ VCC2
−5 V
C3 + C4
0.1 mF 10 mF
CMPWR025
VCC1
VCC2
VOUT
HYS
GND
GND
C5 + C6
0.1 mF 10 mF
Load
11 W
VOUT
Figure 6. Transient Characterization Test Set−Up
Input and Output Capacitors
Filtering is typically unnecessary on the inputs, however
power supply source impedance and parasitic resistance or
inductance on the interconnections may result in chattering
during the supply changeover. When an input is deselected
and the input current drops to zero, the voltage at the input
terminals will rise. If this voltage rise exceeds the hysteresis
(75 mV typical), the switch may chatter.
There are four ways to eliminate this chatter:
1. Connect pin 8 to GND to select 150 mV
hysteresis,
2. position the device as close as possible to the
power supply connectors,
3. use low−impedance PCB traces, or
4. include low−ESR input bypass capacitors at the
VCC1 and VCC2 input pins. Capacitors of 10ĂmF or
greater are recommended.
VOUT provides the power for the load. To ensure the
output is glitch−free during dynamic switching of the inputs,
it is recommended that an external capacitor of 10 mF or
greater is included. This will restrict any transient output
disturbances to less than 300 mV at 600 mA loading during
dynamic switching of the inputs.
The test set−up used in Figure 7 and Figure 8 is described
on page 5. The set−up for Figure 9 has larger series
resistances on VCC1 and VCC2.
VCC1 Rising from 0 V to 5 V/(VCC2 = 5 V). Figure 7
shows the primary supply VCC1 becoming selected during
a 0 V to 5 V transition. The secondary supply VCC2 is set to
5 V DC. The channel 1 switch is turned on when VCC1 rises
to within about 70 mV of VCC2. VCC1 drops when it is
selected due to power supply source resistance RS1.
A positive glitch appears on VCC2 when channel 2 switch is
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