MC54/74HC160A MC54/74HC162A
HC160A, HC162A TIMING DIAGRAM
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit.
RESET (HC160A)
RESET (HC162A)
LOAD
(ASYNCHRONOUS)
(SYNCHRONOUS)
P0
PRESET P1
DATA
INPUTS P2
P3
CLOCK
(HC160A)
CLOCK
(HC162A)
COUNT
ENABLES
ENABLE P
ENABLE T
Q0
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
7 89 0 1 2
3
COUNT
RESET LOAD
INHIBIT
High–Speed CMOS Logic Data
9
DL129 — Rev 6
MOTOROLA