SC28L92A1A View Datasheet(PDF) - Philips Electronics

Part Name

Description

MFG CO.

SC28L92A1A

3.3V–5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART)

Philips Electronics 

Philips Semiconductors

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

Product specification

SC28L92

PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA®)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SYMBOL TYPE

NAME AND FUNCTION

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I/M

I Bus Configuration: When low configures the bus interface to the Conditions shown in this table.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ D0–D7

I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the

CPU. D0 is the least significant bit.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CEN

I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on

D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ R/WN

I Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IACKN

I Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in

response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DACKN

O Data Transfer Acknowledge: A3-State active -low output asserted in a write, read, or interrupt acknowledge cycle to

indicate proper transfer of data between the CPU and the DUART.

A0–A3

I Address Inputs: Select the DUART internal registers and ports for read/write operations.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RESETN

I Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,

stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark

(High) state. Sets MR pointer to MR1. See Figure 4

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ INTRN

O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable

interrupting conditions are true. This pin requires a pullup.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ X1/CLK

I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When

a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

X2

O Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxDA

I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxDB

I Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxDA

O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark”

condition when the transmitter is disabled, idle or when operating in local loop back mode. “Mark” is High; “space” is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TxDB

O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’

condition when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP0

O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated

automatically on receive or transmit.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP1

O Output 1: General-purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated

automatically on receive or transmit.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP2

O Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock

output.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP3

O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock

output, or Channel B receiver 1X clock output.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP4

O Output 4: General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR [1] output.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP5

O Output 5: General-purpose output or Channel B open-drain, active-Low, RxB interrupt ISR[5] output.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP6

O Output 6: General purpose output or Channel A open-drain, active-Low, TxA interrupt ISR[0] output.

OP7

O Output 7: General-purpose output, or Channel B open-drain, active-Low, TxB interrupt ISR[4] output.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IP0

I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN).

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IP1

I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN).

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IP2

I Input 2: General-purpose input or counter/timer external clock input.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IP3

I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ by the transmitter, the transmitted data is clocked on the falling edge of the clock.

IP4

I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ the receiver, the received data is sampled on the rising edge of the clock.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IP5

I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ by the transmitter, the transmitted data is clocked on the falling edge of the clock.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VCC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ GND

Pwr Power Supply: +3.3 or +5V supply input ±10%

Pwr Ground

2000 Jan 21

9

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