SI5340A-A-GM View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
SI5340A-A-GM Datasheet PDF : 48 Pages
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Si5341/40
Table 5. Differential Clock Output Specifications (Continued)
(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Output Voltage Swing1
Symbol
Test Condition
Min Typ Max
Normal Swing Mode
Units
VOUT
VDDO = 3.3 V,
2.5 V, or 1.8 V
LVDS
LVPECL
370 470 570 mVpp_se
650 820 1050
High Swing Mode
VOUT VDDO = 3.3 V,
2.5 V, or 1.8 V
LVDS
310 420 530 mVpp_se
Common Mode Voltage1, 2, 3
VDDO = 3.3 V LVPECL
or 2.5 V
590 830 1060
Normal Swing or High Swing Modes
VCM VDDO = 3.3 V
LVDS
1.12 1.23 1.34
V
LVPECL 1.90 2.0 2.13
VDDO = 2.5 V
LVPECL
LVDS
1.17 1.23 1.3
Rise and Fall Times
tR/tF
(20% to 80%)
Differential Output Impedance4
ZO
Normal Swing Mode
High Swing Mode
Normal Swing Mode
High Swing Mode
— 170 220
ps
— 250 320
— 100 —
— Hi-Z —
Notes:
1. Normal swing mode, high swing mode, Vswing and Cmode settings are programmable through register settings and
can be stored in NVM. Each output driver can be programmed independently.
2. Not all combinations of voltage swing and common mode voltages settings are possible.
3. Common mode voltage min/max variation = ±4% from typical value
4. Driver output impedance depends on selected output mode (Normal, High).
5. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/
3.3 V = 100 mVpp) and noise spur amplitude measured.
OUTx
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vcm
Vpp_diff = 2*Vpp_se
8
Preliminary Rev. 0.9
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