CS5166 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
CS5166 Datasheet PDF : 25 Pages
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CS5166
Duty Cycle =
VOUT ) (ILOAD RDSON OF SYNCH FET)
ƪ ƫ VIN)(ILOAD RDSON OF SYNCH FET)
* (ILOAD RDSON OF SWITCH FET)
Off Time Capacitor (COFF)
The COFF timing capacitor sets the regulator off time:
TOFF + COFF 4848.5
The preceding equations for duty cycle can also be used
to calculate the regulator switching frequency and select the
COFF timing capacitor:
COFF + Perioid
(1 * duty cycle)
4848.5
where:
Period
+
1
switching frequency
Schottky Diode for Synchronous FET
For synchronous operation, a Schottky diode may be
placed in parallel with the synchronous FET to conduct the
inductor current upon turn off of the switching FET to
improve efficiency. The CS5166 reference circuit does not
use this device due to it’s excellent design. Instead, the
body diode of the synchronous FET is utilized to reduce
cost and conducts the inductor current. For a design
operating at 200 kHz or so, the low non−overlap time
combined with Schottky forward recovery time may make
the benefits of this device not worth the additional expense.
The power dissipation in the synchronous MOSFET due to
body diode conduction can be estimated by the following
equation:
Power + VBD ILOAD conduction time switching frequency
Where VBD = the forward drop of the MOSFET body
diode. For the CS5166 demonstration board:
Power + 1.6 V 14.2 A 100 ns 200 kHz + 0.45 W
This is only 1.1% of the 40 W being delivered to the load.
“Droop” Resistor for Adaptive Voltage Positioning
Adaptive voltage positioning is used to help keep the
output voltage within specification during load transients.
To implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the full
load current and should be chosen so that both DC and AC
tolerance limits are met. An embedded PC trace resistor has
the distinct advantage of near zero cost implementation.
However, this droop resistor can vary due to three reasons:
1) the sheet resistivity variation causes the thickness of the
PCB layer to vary. 2) the mismatch of L/W, and 3)
temperature variation.
1. Sheet Resistivity for one ounce copper, the thickness
variation typically 1.15 mil to 1.35 mil. Therefore the
error due to sheet resistivity is:
1.35 * 1.15
1.25
+
16%
2. Mismatch due to L/W. The variation in L/W is
governed by variations due to the PCB manufacturing
process that affect the geometry and the power
dissipation capability of the droop resistor. The error
due to L/W mismatch is typically 1.0%.
3. Thermal Considerations. Due to I2 × R power losses
the surface temperature of the droop resistor will
increase causing the resistance to increase. Also, the
ambient temperature variation will contribute to the
increase of the resistance, according to the formula:
R + R20[1 ) a20(T * 20)]
where:
R20 = resistance at 20°C
a
+
0.00393
°C
T = operating temperature
R = desired droop resistor value
For temperature T = 50°C, the % R change = 12%
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation
Tolerance due to L/W error
Tolerance due to temperature variation
Total tolerance for droop resistor
16%
1.0%
12%
29%
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage full load
is above the minimum DC tolerance spec.
VDROOP(TYP)
+
[VDAC(MIN) * VDC(MIN)]
1 ) RDROOP(TOLERANCE)
Example: for a 300 MHz PentiumII, the DC accuracy spec
is 2.74 < VCC(CORE) < 2.9 V, and the AC accuracy spec is
2.67 V < VCC(CORE) < 2.93 V. The CS5166 DAC output
voltage is +2.796 V < VDAC < +2.853 V. In order not to
exceed the DC accuracy spec, the voltage drop developed
across the resistor must be calculated as follows:
VDROOP(TYP)
+
[VDAC(MIN) * VDC PENTIUMII(MIN)]
1 ) RDROOP(TOLERANCE)
+
2.796
V*
1.3
2.74
V
+
43
mV
With the CS5166 DAC accuracy being 1.0%, the internal
error amplifier’s reference voltage is trimmed so that the
output voltage will be 25 mV high at no load. With no load,
there is no DC drop across the resistor, producing an output
voltage tracking the error amplifier output voltage,
including the offset. When the full load current is delivered,
a drop of −43 mV is developed across the resistor. Therefore,
the regulator output is pre−positioned at 25 mV above the
nominal output voltage before a load turn−on. The total
voltage drop due to a load step is ΔV−25 mV and the
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