AD7871JN View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7871JN Datasheet PDF : 24 Pages
| |||
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7871/AD7872
CONVST 1
CS 2
RD 3
BUSY/INT 4
CLK 5
DB13/HBEN 6
DB12/SSTRB 7
DB11/SCLK 8
DB10/SDATA 9
DB9 10
DB8 11
DB7 12
DB6 13
DGND 14
AD7871
TOP VIEW
(Not to Scale)
28 14/8/CLK
27 VSS
26 VIN
25 REFOUT
24 NC
23 CREF
22 AGND
21 VDD
20 DB0/DB8
19 DB1/DB9
18 DB2/DB10
17 DB3/DB11
16 DB4/DB12
15 DB5/DB13
NOTES
1. NC = NO CONNECT.
Figure 5. AD7871 DIP
4 3 2 1 28 27 26
CLK 5
DB13/HBEN 6
DB12/SSTRB 7
DB11/SCLK 8
DB10/SDATA 9
DB9 10
DB8 11
AD7871
TOP VIEW
(Not to Scale)
25 REFOUT
24 NC
23 CREF
22 AGND
21 VDD
20 DB0/DB8
19 DB1/DB9
12 13 14 15 16 17 18
NOTES
1. NC = NO CONNECT.
Figure 6. AD7871 PLCC
Table 4. AD7871 Pin Function Descriptions
Pin No. Mnemonic Description
1
CONVST
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This input is
asynchronous to the CLK. CS and RD must be held high for the duration of this pulse.
2
CS
Chip Select. Active low logic input. The device is selected when this input is active. With CONVST tied low, a new
conversion is initiated when CS goes low.
3
RD
Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.
4
BUSY/INT Busy/Interrupt. Logic low output indicating converter status. See Figure 14, Figure 15, Figure 16, and Figure 17.
5
CLK
Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS
enables the internal laser-trimmed oscillator.
6
DB13/HBEN Data Bit 13 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 14/8/CLK input (see
Pin 28). When 14-bit data is selected, this pin provides the DB13 output. When either byte or serial data is
selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7 to
DB0 is the lower byte of data. With HBEN high, DB7 to DB0 is the upper byte of data (see Table 5).
7
DB12/SSTRB Data Bit 12/Serial Strobe. When 14-bit data is selected, this pin provides the DB12 data output. Otherwise, it is an
active low three-state output that provides a framing pulse for serial data.
8
DB11/SCLK Data Bit 11/Serial Clock. When 14-bit data is selected, this pin provides the DB11 data output. Otherwise, SCLK is
the gated serial clock output that is derived from the internal or external ADC clock. If the 14/8/CLK input is held
at −5 V, then the SCLK runs continuously. With 14/8/CLK at 0 V, it is gated off (three-state) after serial transmission
is complete.
9
DB10/SDATA Data Bit 10/Serial Data. When 14-bit parallel data is selected, this pin provides the DB10 data output. Otherwise, it
is the three-state serial data output used in conjunction with SCLK and SSTRB in serial data transmission. Serial
data is valid on the falling edge of SCLK, when SSTRB is low.
10 to 13 DB9 to DB6
Three-State Data Outputs controlled by CS and RD. Their function depends on the state of the 14/8/CLK and the
HBEN inputs. With 14/8/CLK high, they are always DB9 to DB6; with 14/8/CLK low, their function depends on
HBEN (see Table 5).
14
DGND
Digital Ground. Ground return for digital circuitry.
15 to 20 DB5/DB13
to DB0/DB8
Three-State Data Outputs controlled by CS and RD. Their function depends on the 14/8/CLK DB0/DB8 and HBEN
inputs. With 14/8/CLK high, they are always DB5 to DB0; with 14/8/C LK low or −5 V, their function is controlled by
HBEN (see Table 5).
21
VDD
Positive Supply, +5 V ± 5%.
22
AGND
Analog Ground. Ground reference for analog circuitry.
23
CREF
Decoupling Point for On-Chip Reference. Connect a 10 nF capacitor between this pin and AGND.
24
NC
No Connect.
25
REFOUT
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is 500 µA.
Rev. E | Page 7 of 24
Share Link: 