AD7871 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7871 Datasheet PDF : 24 Pages
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Data Sheet
TIMING AND CONTROL
The conversion time for both external and internal clocks can
vary from 19 to 20 rising clock edges depending on the
conversion start to ADC clock synchronization. If a conversion
is initiated within 30 ns prior to a rising edge of the ADC clock,
the conversion time will consist of 20 rising clock edges.
There are two basic operating modes for the AD7871. In the
first mode (Mode 1), the CONVST line is used to start a
conversion and drive the track/hold into its hold mode. At the
end of the conversion, the track/hold returns to its tracking
mode. It is principally intended for digital signal processing and
other applications where precise sampling in time is required.
In these applications, it is important that the signal sampling
occurs at exactly equal intervals to minimize errors due to
sampling uncertainty or jitter. For these cases, the CONVST
line is driven by a timer or some precise clock source.
The second mode is achieved by hard-wiring the CONVST line
low. This mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS and RD start a
conversion, and the microprocessor will normally be driven
into a wait state for the duration of conversion by BUSY/INT.
The AD7872 has one operating mode only: Mode 1, which
uses CONVST to start conversion.
DATA OUTPUT FORMATS
The AD7871 offers a choice of three data output formats: one
serial and two parallel. The parallel data formats include a
single 14-bit parallel word for 16-bit data buses and a two-byte
format for 8-bit data buses. The data format is controlled by the
14/8/CLK input. A logic high on this pin selects the 14-bit
parallel output format only. A logic low or −5 V applied to this
pin allows the user access to either serial or byte formatted data.
Three of the pins previously assigned to the four MSBs in
parallel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
The three possible data output formats can be selected in either
of the modes of operation.
The AD7872 is a serial output device only. The serial data
format is exactly the same as the AD7871.
AD7871/AD7872
Parallel Output Format
The two parallel formats available on the AD7871 are a 14-bit
wide data word and a 2-byte data word. In the first, all 14 bits of
data are available at the same time on DB13 (MSB) through
DB0 (LSB). In the second, two reads are required to access the
data. When this data format is selected, the DB13/HBEN pin
assumes the HBEN function. HBEN selects which byte of data
is to be read from the AD7871. When HBEN is low, the lower
eight bits of data are placed on the data bus during a read
operation; with HBEN high, the upper six bits of the 14-bit
word are placed on the data bus. These six bits are right justified
and thereby occupy the lower six bits of the byte while the
upper two bits are zeros.
Serial Output Format
Serial data is available on the AD7871 when the 14/8/CLK input
is at 0 V or −5 V and in this case the DB12/SSTRB, DB11/SCLK
and DB10/SDATA pins assume their serial functions. The
AD7872 is a serial output device only. The serial function on
both devices is identical. Serial data is available during
conversion with a word length of 16 bits; two leading zeros,
followed by the 14-bit conversion result starting with the MSB.
The data is synchronized to the serial clock output (SCLK) and
is framed by the serial strobe (SSTRB). Data is clocked out on a
low to high transition of the serial clock and is valid on the
falling edge of this clock while the SSTRB output is low. SSTRB
goes low at the start of conversion and the first serial data bit
(which is the first leading zero) is valid on the first falling edge
of SCLK. All the serial lines are open-drain outputs and require
external pull-up resistors.
The serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, SCLK is
required during the serial transmission only. In these cases it
can be shut down (that is, placed into three-state) at the end of
the conversion to allow multiple ADCs to share a common
serial bus. However, some serial systems require a serial clock
that runs continuously. Both options are available on the
AD7871 and AD7872. With the 14/8/CLK input on the
AD7871 at −5 V, the serial clock (SCLK) runs continuously;
when 14/8/CLK is at 0 V, SCLK goes into three-state at the end
of transmission. The CONTROL pin on the AD7872 performs
the same function. When this is at 0 V, SCLK is noncontinuous
and when it is at −5 V, SCLK is continuous.
The SCLK, SDATA, and SSTRB lines are open-drain outputs. If
these are required to drive capacitive loads in excess of 35 pF,
buffering is recommended.
Rev. E | Page 11 of 24
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