AD5304ACPZ-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD5304ACPZ-REEL7
Analog Devices
AD5304ACPZ-REEL7 Datasheet PDF : 24 Pages
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Data Sheet
Opto-Isolated Interface for Process Control Applications
The AD5304/AD5314/AD5324 have a versatile 3-wire serial
inter-face, making them ideal for generating accurate voltages
in process control and industrial applications. Due to noise,
safety requirements, or distance, it might be necessary to isolate
the AD5304/AD5314/AD5324 from the controller. This can
easily be achieved by using opto-isolators, which provide isolation
in excess of 3 kV. The actual data rate achieved is limited by the
type of optocouplers chosen. The serial loading structure of the
AD5304/AD5314/AD5324 makes them ideally suited for use in
opto-isolated applications. Figure 42 shows an opto-isolated
interface to the AD5304 where DIN, SCLK, and SYNC are driven
from optocouplers. The power supply to the part also needs to
be isolated. This is done by using a transformer. On the DAC
side of the transformer, a 5 V regulator provides the 5 V supply
required for the AD5304.
POWER
5V
REGULATOR
10µF
0.1µF
SCLK
VDD
10kΩ
SCLK VDD
REFIN
SYNC
DIN
VDD
10kΩ
VDD
10kΩ
AD5304
SYNC
VOUTA
VOUTB
VOUTC
VOUTD
DIN
GND
Figure 42. AD5304 in an Opto-Isolated Interface
DECODING MULTIPLE AD5304/AD5314/AD5324S
The SYNC pin on the AD5304/AD5314/AD5324 can be used
in applications to decode a number of DACs. In this application, all
the DACs in the system receive the same serial clock and serial
data, but SYNC can only be active to one of the devices at any one
time, allowing access to four channels in this 16-channel system.
The 74HC139 is used as a 2-to-4-line decoder to address any of the
DACs in the system. To prevent timing errors, the enable input
must be brought to its inactive state while the coded address
inputs are changing state. Figure 43 shows a diagram of a typical
setup for decoding multiple AD5304 devices in a system.
AD5304/AD5314/AD5324
SCLK
DIN
ENABLE
CODED
ADDRESS
VDD
VCC
1G 74HC139
1Y0
1A
1Y1
1B
1Y2
1Y3
DGND
AD5304
SYNC
DIN
SCLK
VOUTA
VOUTB
VOUTC
VOUTD
AD5304
SYNC
DIN
SCLK
VOUTA
VOUTB
VOUTC
VOUTD
AD5304
SYNC
DIN
SCLK
VOUTA
VOUTB
VOUTC
VOUTD
AD5304
SYNC
DIN
SCLK
VOUTA
VOUTB
VOUTC
VOUTD
Figure 43. Decoding Multiple AD5304 Devices in a System
AD5304/AD5314/AD5324 as a Digitally Programmable
Window Detector
A digitally programmable upper/lower limit detector using two
DACs in the AD5304/AD5314/AD5324 is shown in Figure 44.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the VIN input is not within the programmed window,
an LED indicates the fail condition. Similarly, DAC C and DAC D
can be used for window detection on a second VIN signal.
5V
0.1µF 10µF
VIN
1kΩ
1kΩ
VREF
SYNC
DIN
SCLK
VDD
REFIN
VOUTA
1/2
AD5304/AD5314/
AD5324*
SYNC
DIN
SCLK
VOUTB
GND
FAIL
PASS
1/2
CMP04
PASS/FAIL
1/6 74HC05
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Window Detection
Rev. H | Page 19 of 24
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