NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
5. Pinning information
5.1 Pinning
+&
+&7
2(
',5
9&&
62
6,
'
'25
4
'
4
'
4
'
4
*1'
05
DDD
Fig 5. Pin configuration DIP16 and SO16
+&
+&7
2(
',5
6,
'
'
'
'
*1'
9&&
62
'25
4
4
4
4
05
DDD
Fig 6. Pin configuration (T)SSOP16
5.2 Pin description
Table 2. Pin description
Symbol Pin
OE
1
DIR
2
SI
3
D0 to D3 4, 5, 6, 7
GND
8
MR
9
Q0 to Q3 13, 12, 11, 10
DOR
14
SO
15
VCC
16
Description
output enable input (active LOW)
data-in-ready output
shift-in input (LOW-to-HIGH, edge triggered)
parallel data input
ground (0 V)
asynchronous master-reset input (active HIGH)
data output
data-out-ready output
shift-out input (HIGH-to-LOW, edge triggered)
supply voltage
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 25 September 2013
© NXP B.V. 2013. All rights reserved.
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