AD7366 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7366 Datasheet PDF : 17 Pages
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AD7366
Preliminary Technical Data
TIMING SPECIFICATIONS
AVCC = DVCC =4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = −11.5 V to −16.5 V, VDRIVE = 2.7 V to 5.25V, TA = TMIN to TMAX, unless
otherwise noted1.
Table 3.
Parameter
tCONVERT
fSCLK
tQUIET
t1
t2
t3
t4
t52
t6
t7
t8
t9
t10
tPOWER-UP
Limit at TMIN, TMAX
2.7V≤VDRIVE<4.75V 4.75V≤VDRIVE≤5.25V
610
610
10
10
35
48
30
30
10
10
5
5
0
0
10
10
20
5
0.1 tSCLK
0.1 tSCLK
10
5
10
70
14
5
0.1 tSCLK
0.1 tSCLK
10
5
10
70
Unit
ns max
kHz min
MHz
max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
μs
Test Conditions / Comments
Conversion time, Internal clock. CONVST falling edge to BUSY falling
edge
Frequency of serial read clock.
Minimum quiet time required between end of serial read and start of
next conversion
Minimum CONVST Low pulse.
CONVST falling edge to BUSY rising edge.
BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going
Low
Delay from CS falling edge until DOUTA and DOUTB are three-state
disabled
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK low pulse width
SCLK high pulse width
CS rising edge to DOUTA, DOUTB, high impedance
SCLK falling edge to DOUTA, DOUTB, high impedance
SCLK falling edge to DOUTA, DOUTB, high impedance
Power up time from shutdown mode. Time required between CONVST
rising edge and CONVST falling edge.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See
Terminology section and Figure 9.
2 The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrG | Page 6 of 17
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